clk/rockchip/clk_rk3588.c

55 	[V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
1096 		parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_get_clk()
1097 					       priv->cru, V0PLL);  in rk3588_dclk_vop_get_clk()
1157 		pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_set_clk()
1158 						 priv->cru, V0PLL);  in rk3588_dclk_vop_set_clk()
1171 			rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_set_clk()
1172 					      priv->cru, V0PLL, div * rate);  in rk3588_dclk_vop_set_clk()
1546 		rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,  in rk3588_clk_get_rate()
1547 					     V0PLL);  in rk3588_clk_get_rate()
1689 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,  in rk3588_clk_set_rate()
1690 					    V0PLL, rate);  in rk3588_clk_set_rate()
1691 		priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_clk_set_rate()
1692 						       priv->cru, V0PLL);  in rk3588_clk_set_rate()