65 	[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
1516 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_get_rate()
1517 						      priv->cru, PPLL);  in rk3588_clk_get_rate()
1554 		rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_get_rate()
1555 					     PPLL);  in rk3588_clk_get_rate()
1667 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_set_rate()
1668 						      priv->cru, PPLL);  in rk3588_clk_set_rate()
1701 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_set_rate()
1702 					    PPLL, rate);  in rk3588_clk_set_rate()
1703 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_set_rate()
1704 						      priv->cru, PPLL);  in rk3588_clk_set_rate()
2047 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,  in rk3588_clk_init()
2048 					    PPLL, PPLL_HZ);  in rk3588_clk_init()
2049 		priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],  in rk3588_clk_init()
2050 						      priv->cru, PPLL);  in rk3588_clk_init()