Lines Matching full:rate
153 u32 con, sel, rate; in rk3588_center_get_clk() local
161 rate = 702 * MHz; in rk3588_center_get_clk()
163 rate = 396 * MHz; in rk3588_center_get_clk()
165 rate = 200 * MHz; in rk3588_center_get_clk()
167 rate = OSC_HZ; in rk3588_center_get_clk()
174 rate = 500 * MHz; in rk3588_center_get_clk()
176 rate = 250 * MHz; in rk3588_center_get_clk()
178 rate = 100 * MHz; in rk3588_center_get_clk()
180 rate = OSC_HZ; in rk3588_center_get_clk()
187 rate = 396 * MHz; in rk3588_center_get_clk()
189 rate = 200 * MHz; in rk3588_center_get_clk()
191 rate = 100 * MHz; in rk3588_center_get_clk()
193 rate = OSC_HZ; in rk3588_center_get_clk()
200 rate = 200 * MHz; in rk3588_center_get_clk()
202 rate = 100 * MHz; in rk3588_center_get_clk()
204 rate = 50 * MHz; in rk3588_center_get_clk()
206 rate = OSC_HZ; in rk3588_center_get_clk()
212 return rate; in rk3588_center_get_clk()
216 ulong clk_id, ulong rate) in rk3588_center_set_clk() argument
223 if (rate >= 700 * MHz) in rk3588_center_set_clk()
225 else if (rate >= 396 * MHz) in rk3588_center_set_clk()
227 else if (rate >= 200 * MHz) in rk3588_center_set_clk()
236 if (rate >= 500 * MHz) in rk3588_center_set_clk()
238 else if (rate >= 250 * MHz) in rk3588_center_set_clk()
240 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
249 if (rate >= 396 * MHz) in rk3588_center_set_clk()
251 else if (rate >= 198 * MHz) in rk3588_center_set_clk()
253 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
262 if (rate >= 198 * MHz) in rk3588_center_set_clk()
264 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
266 else if (rate >= 50 * MHz) in rk3588_center_set_clk()
285 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
314 rate = 100 * MHz; in rk3588_top_get_clk()
316 rate = 50 * MHz; in rk3588_top_get_clk()
318 rate = OSC_HZ; in rk3588_top_get_clk()
324 return rate; in rk3588_top_get_clk()
328 ulong clk_id, ulong rate) in rk3588_top_set_clk() argument
335 if (!(priv->cpll_hz % rate)) { in rk3588_top_set_clk()
337 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
340 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
351 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
361 if (rate == 100 * MHz) in rk3588_top_set_clk()
363 else if (rate == 50 * MHz) in rk3588_top_set_clk()
383 ulong rate; in rk3588_i2c_get_clk() local
426 rate = 200 * MHz; in rk3588_i2c_get_clk()
428 rate = 100 * MHz; in rk3588_i2c_get_clk()
430 return rate; in rk3588_i2c_get_clk()
434 ulong rate) in rk3588_i2c_set_clk() argument
439 if (rate >= 198 * MHz) in rk3588_i2c_set_clk()
528 ulong clk_id, ulong rate) in rk3588_spi_set_clk() argument
533 if (rate >= 198 * MHz) in rk3588_spi_set_clk()
535 else if (rate >= 140 * MHz) in rk3588_spi_set_clk()
612 ulong clk_id, ulong rate) in rk3588_pwm_set_clk() argument
617 if (rate >= 99 * MHz) in rk3588_pwm_set_clk()
619 else if (rate >= 50 * MHz) in rk3588_pwm_set_clk()
685 ulong clk_id, ulong rate) in rk3588_adc_set_clk() argument
692 if (!(OSC_HZ % rate)) { in rk3588_adc_set_clk()
693 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
703 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
715 if (!(OSC_HZ % rate)) { in rk3588_adc_set_clk()
716 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
726 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
811 ulong clk_id, ulong rate) in rk3588_mmc_set_clk() argument
820 if (!(OSC_HZ % rate)) { in rk3588_mmc_set_clk()
822 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_mmc_set_clk()
823 } else if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
825 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
828 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
832 if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
834 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
837 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
841 if (!(702 * MHz % rate)) { in rk3588_mmc_set_clk()
843 div = DIV_ROUND_UP(702 * MHz, rate); in rk3588_mmc_set_clk()
846 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
918 ulong clk_id, ulong rate) in rk3588_aux16m_set_clk() argument
928 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aux16m_set_clk()
997 ulong clk_id, ulong rate) in rk3588_aclk_vop_set_clk() argument
1005 if (rate >= 850 * MHz) { in rk3588_aclk_vop_set_clk()
1008 } else if (rate >= 750 * MHz) { in rk3588_aclk_vop_set_clk()
1011 } else if (rate >= 700 * MHz) { in rk3588_aclk_vop_set_clk()
1014 } else if (!(priv->cpll_hz % rate)) { in rk3588_aclk_vop_set_clk()
1016 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_aclk_vop_set_clk()
1019 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aclk_vop_set_clk()
1028 if (rate == 400 * MHz || rate == 396 * MHz) in rk3588_aclk_vop_set_clk()
1030 else if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1032 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1041 if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1043 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1045 else if (rate == 50 * MHz) in rk3588_aclk_vop_set_clk()
1109 ulong clk_id, ulong rate) in rk3588_dclk_vop_set_clk() argument
1159 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1160 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1166 div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); in rk3588_dclk_vop_set_clk()
1172 priv->cru, V0PLL, div * rate); in rk3588_dclk_vop_set_clk()
1194 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1198 if (abs(rate - now) < abs(rate - best_rate)) { in rk3588_dclk_vop_set_clk()
1213 printf("do not support this vop freq %lu\n", rate); in rk3588_dclk_vop_set_clk()
1248 ulong clk_id, ulong rate) in rk3588_gmac_set_clk() argument
1253 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_gmac_set_clk()
1350 ulong clk_id, ulong rate) in rk3588_uart_set_rate() argument
1356 if (priv->gpll_hz % rate == 0) { in rk3588_uart_set_rate()
1359 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1360 } else if (priv->cpll_hz % rate == 0) { in rk3588_uart_set_rate()
1363 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1364 } else if (rate == OSC_HZ) { in rk3588_uart_set_rate()
1372 rational_best_approximation(rate, priv->gpll_hz / div, in rk3588_uart_set_rate()
1460 ulong clk_id, ulong rate) in rk3588_pciephy_set_rate() argument
1465 if (rate == OSC_HZ) { in rk3588_pciephy_set_rate()
1470 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3588_pciephy_set_rate()
1508 ulong rate = 0; in rk3588_clk_get_rate() local
1522 rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru, in rk3588_clk_get_rate()
1526 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru, in rk3588_clk_get_rate()
1530 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru, in rk3588_clk_get_rate()
1534 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1538 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1542 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1546 rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_get_rate()
1550 rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru, in rk3588_clk_get_rate()
1554 rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_get_rate()
1561 rate = rk3588_center_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1566 rate = rk3588_top_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1577 rate = rk3588_i2c_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1584 rate = rk3588_spi_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1590 rate = rk3588_pwm_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1594 rate = rk3588_adc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1601 rate = rk3588_mmc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1604 rate = OSC_HZ; in rk3588_clk_get_rate()
1615 rate = rk3588_aclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1624 rate = rk3588_dclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1630 rate = rk3588_gmac_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1641 rate = rk3588_uart_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1646 rate = rk3588_pciephy_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1653 return rate; in rk3588_clk_get_rate()
1656 static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) in rk3588_clk_set_rate() argument
1674 CPLL, rate); in rk3588_clk_set_rate()
1680 GPLL, rate); in rk3588_clk_set_rate()
1686 NPLL, rate); in rk3588_clk_set_rate()
1690 V0PLL, rate); in rk3588_clk_set_rate()
1696 AUPLL, rate); in rk3588_clk_set_rate()
1702 PPLL, rate); in rk3588_clk_set_rate()
1710 ret = rk3588_center_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1715 ret = rk3588_top_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1726 ret = rk3588_i2c_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1733 ret = rk3588_spi_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1739 ret = rk3588_pwm_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1743 ret = rk3588_adc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1750 ret = rk3588_mmc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1758 rk3588_aux16m_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1764 ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1773 ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1779 ret = rk3588_gmac_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1790 ret = rk3588_uart_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1795 ret = rk3588_pciephy_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1823 ulong rate; in rk3588_mmc_get_phase() local
1825 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_get_phase()
1826 if (rate <= 0) in rk3588_mmc_get_phase()
1827 return rate; in rk3588_mmc_get_phase()
1840 36 * (rate / 1000000); in rk3588_mmc_get_phase()
1856 ulong rate; in rk3588_mmc_set_phase() local
1858 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_set_phase()
1859 if (rate <= 0) in rk3588_mmc_set_phase()
1860 return rate; in rk3588_mmc_set_phase()
1871 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3588_mmc_set_phase()
2311 static ulong rk3588_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3588_clk_scmi_set_rate() argument
2326 if (rate >= 700 * MHz) in rk3588_clk_scmi_set_rate()
2338 if ((OSC_HZ % rate) == 0) { in rk3588_clk_scmi_set_rate()
2339 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_clk_scmi_set_rate()
2343 } else if ((SPLL_RATE % rate) == 0) { in rk3588_clk_scmi_set_rate()
2344 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2349 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2356 if ((SPLL_RATE % rate) == 0) { in rk3588_clk_scmi_set_rate()
2357 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2362 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2369 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2371 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2373 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2382 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2384 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2386 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2395 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2397 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2399 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2408 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2410 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2412 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2421 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2423 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2425 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2437 if (rate >= 150 * MHz) in rk3588_clk_scmi_set_rate()
2439 else if (rate >= 100 * MHz) in rk3588_clk_scmi_set_rate()
2441 else if (rate >= 50 * MHz) in rk3588_clk_scmi_set_rate()
2481 unsigned long rate; in soc_clk_dump() local
2509 rate = clk_get_rate(&clk); in soc_clk_dump()
2511 if (rate < 0) in soc_clk_dump()
2516 rate / 1000); in soc_clk_dump()