Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
9 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3588-cru.h>
22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
101 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
152 struct rk3588_cru *cru = priv->cru; in rk3588_center_get_clk()
157 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
170 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
183 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
196 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
209 return -ENOENT; in rk3588_center_get_clk()
218 struct rk3588_cru *cru = priv->cru; in rk3588_center_set_clk()
231 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
244 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
257 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
270 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
276 return -EINVAL; in rk3588_center_set_clk()
284 struct rk3588_cru *cru = priv->cru; in rk3588_top_get_clk()
285 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
289 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
290 div = (con & ACLK_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
295 prate = priv->cpll_hz; in rk3588_top_get_clk()
297 prate = priv->gpll_hz; in rk3588_top_get_clk()
298 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
300 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
301 div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
306 prate = priv->cpll_hz; in rk3588_top_get_clk()
308 prate = priv->gpll_hz; in rk3588_top_get_clk()
309 return DIV_TO_RATE(prate, div); in rk3588_top_get_clk()
311 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
321 return -ENOENT; in rk3588_top_get_clk()
330 struct rk3588_cru *cru = priv->cru; in rk3588_top_set_clk()
335 if (!(priv->cpll_hz % rate)) { in rk3588_top_set_clk()
337 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
340 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
342 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
343 rk_clrsetreg(&cru->clksel_con[8], in rk3588_top_set_clk()
348 (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
351 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
352 assert(src_clk_div - 1 <= 31); in rk3588_top_set_clk()
353 rk_clrsetreg(&cru->clksel_con[8], in rk3588_top_set_clk()
358 (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT); in rk3588_top_set_clk()
367 rk_clrsetreg(&cru->clksel_con[8], in rk3588_top_set_clk()
373 return -EINVAL; in rk3588_top_set_clk()
381 struct rk3588_cru *cru = priv->cru; in rk3588_i2c_get_clk()
387 con = readl(&cru->pmuclksel_con[3]); in rk3588_i2c_get_clk()
391 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
395 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
399 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
403 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
407 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
411 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
415 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
419 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
423 return -ENOENT; in rk3588_i2c_get_clk()
436 struct rk3588_cru *cru = priv->cru; in rk3588_i2c_set_clk()
446 rk_clrsetreg(&cru->pmuclksel_con[3], CLK_I2C0_SEL_MASK, in rk3588_i2c_set_clk()
450 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C1_SEL_MASK, in rk3588_i2c_set_clk()
454 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C2_SEL_MASK, in rk3588_i2c_set_clk()
458 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C3_SEL_MASK, in rk3588_i2c_set_clk()
462 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C4_SEL_MASK, in rk3588_i2c_set_clk()
466 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C5_SEL_MASK, in rk3588_i2c_set_clk()
470 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C6_SEL_MASK, in rk3588_i2c_set_clk()
474 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C7_SEL_MASK, in rk3588_i2c_set_clk()
478 rk_clrsetreg(&cru->clksel_con[38], CLK_I2C8_SEL_MASK, in rk3588_i2c_set_clk()
482 return -ENOENT; in rk3588_i2c_set_clk()
490 struct rk3588_cru *cru = priv->cru; in rk3588_spi_get_clk()
493 con = readl(&cru->clksel_con[59]); in rk3588_spi_get_clk()
512 return -ENOENT; in rk3588_spi_get_clk()
523 return -ENOENT; in rk3588_spi_get_clk()
530 struct rk3588_cru *cru = priv->cru; in rk3588_spi_set_clk()
542 rk_clrsetreg(&cru->clksel_con[59], in rk3588_spi_set_clk()
547 rk_clrsetreg(&cru->clksel_con[59], in rk3588_spi_set_clk()
552 rk_clrsetreg(&cru->clksel_con[59], in rk3588_spi_set_clk()
557 rk_clrsetreg(&cru->clksel_con[59], in rk3588_spi_set_clk()
562 rk_clrsetreg(&cru->clksel_con[59], in rk3588_spi_set_clk()
567 return -ENOENT; in rk3588_spi_set_clk()
575 struct rk3588_cru *cru = priv->cru; in rk3588_pwm_get_clk()
580 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
584 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
588 con = readl(&cru->clksel_con[60]); in rk3588_pwm_get_clk()
592 con = readl(&cru->pmuclksel_con[2]); in rk3588_pwm_get_clk()
596 return -ENOENT; in rk3588_pwm_get_clk()
607 return -ENOENT; in rk3588_pwm_get_clk()
614 struct rk3588_cru *cru = priv->cru; in rk3588_pwm_set_clk()
626 rk_clrsetreg(&cru->clksel_con[59], in rk3588_pwm_set_clk()
631 rk_clrsetreg(&cru->clksel_con[59], in rk3588_pwm_set_clk()
636 rk_clrsetreg(&cru->clksel_con[60], in rk3588_pwm_set_clk()
641 rk_clrsetreg(&cru->pmuclksel_con[2], in rk3588_pwm_set_clk()
646 return -ENOENT; in rk3588_pwm_set_clk()
654 struct rk3588_cru *cru = priv->cru; in rk3588_adc_get_clk()
655 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
659 con = readl(&cru->clksel_con[40]); in rk3588_adc_get_clk()
660 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3588_adc_get_clk()
666 prate = priv->gpll_hz; in rk3588_adc_get_clk()
667 return DIV_TO_RATE(prate, div); in rk3588_adc_get_clk()
669 con = readl(&cru->clksel_con[41]); in rk3588_adc_get_clk()
670 div = (con & CLK_TSADC_DIV_MASK) >> in rk3588_adc_get_clk()
678 return DIV_TO_RATE(prate, div); in rk3588_adc_get_clk()
680 return -ENOENT; in rk3588_adc_get_clk()
687 struct rk3588_cru *cru = priv->cru; in rk3588_adc_set_clk()
694 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
695 rk_clrsetreg(&cru->clksel_con[40], in rk3588_adc_set_clk()
700 (src_clk_div - 1) << in rk3588_adc_set_clk()
703 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
704 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
705 rk_clrsetreg(&cru->clksel_con[40], in rk3588_adc_set_clk()
710 (src_clk_div - 1) << in rk3588_adc_set_clk()
717 assert(src_clk_div - 1 <= 255); in rk3588_adc_set_clk()
718 rk_clrsetreg(&cru->clksel_con[41], in rk3588_adc_set_clk()
723 (src_clk_div - 1) << in rk3588_adc_set_clk()
726 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
727 assert(src_clk_div - 1 <= 7); in rk3588_adc_set_clk()
728 rk_clrsetreg(&cru->clksel_con[41], in rk3588_adc_set_clk()
733 (src_clk_div - 1) << in rk3588_adc_set_clk()
738 return -ENOENT; in rk3588_adc_set_clk()
745 struct rk3588_cru *cru = priv->cru; in rk3588_mmc_get_clk()
746 u32 sel, con, div, prate; in rk3588_mmc_get_clk() local
750 con = readl(&cru->clksel_con[172]); in rk3588_mmc_get_clk()
751 div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT; in rk3588_mmc_get_clk()
755 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
757 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
760 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
762 con = readl(&cru->clksel_con[77]); in rk3588_mmc_get_clk()
763 div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
767 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
769 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
772 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
774 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
775 div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
779 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
781 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
782 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
784 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
785 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rk3588_mmc_get_clk()
789 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
791 prate = priv->cpll_hz; in rk3588_mmc_get_clk()
794 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
796 con = readl(&cru->clksel_con[62]); in rk3588_mmc_get_clk()
797 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; in rk3588_mmc_get_clk()
803 prate = priv->gpll_hz; in rk3588_mmc_get_clk()
804 return DIV_TO_RATE(prate, div); in rk3588_mmc_get_clk()
806 return -ENOENT; in rk3588_mmc_get_clk()
813 struct rk3588_cru *cru = priv->cru; in rk3588_mmc_set_clk()
814 int src_clk, div; in rk3588_mmc_set_clk() local
822 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_mmc_set_clk()
823 } else if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
825 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
828 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
832 if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
834 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
837 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
843 div = DIV_ROUND_UP(702 * MHz, rate); in rk3588_mmc_set_clk()
846 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
850 return -ENOENT; in rk3588_mmc_set_clk()
855 rk_clrsetreg(&cru->clksel_con[172], in rk3588_mmc_set_clk()
859 (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT); in rk3588_mmc_set_clk()
862 rk_clrsetreg(&cru->clksel_con[77], in rk3588_mmc_set_clk()
866 (div - 1) << CCLK_EMMC_DIV_SHIFT); in rk3588_mmc_set_clk()
869 rk_clrsetreg(&cru->clksel_con[78], in rk3588_mmc_set_clk()
873 (div - 1) << BCLK_EMMC_DIV_SHIFT); in rk3588_mmc_set_clk()
876 rk_clrsetreg(&cru->clksel_con[78], in rk3588_mmc_set_clk()
880 (div - 1) << SCLK_SFC_DIV_SHIFT); in rk3588_mmc_set_clk()
883 rk_clrsetreg(&cru->clksel_con[62], in rk3588_mmc_set_clk()
887 (div - 1) << DCLK_DECOM_DIV_SHIFT); in rk3588_mmc_set_clk()
890 return -ENOENT; in rk3588_mmc_set_clk()
899 struct rk3588_cru *cru = priv->cru; in rk3588_aux16m_get_clk()
900 u32 div, con, parent; in rk3588_aux16m_get_clk() local
902 parent = priv->gpll_hz; in rk3588_aux16m_get_clk()
903 con = readl(&cru->clksel_con[117]); in rk3588_aux16m_get_clk()
907 div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT; in rk3588_aux16m_get_clk()
908 return DIV_TO_RATE(parent, div); in rk3588_aux16m_get_clk()
910 div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT; in rk3588_aux16m_get_clk()
911 return DIV_TO_RATE(parent, div); in rk3588_aux16m_get_clk()
913 return -ENOENT; in rk3588_aux16m_get_clk()
920 struct rk3588_cru *cru = priv->cru; in rk3588_aux16m_set_clk()
921 u32 div; in rk3588_aux16m_set_clk() local
923 if (!priv->gpll_hz) { in rk3588_aux16m_set_clk()
924 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rk3588_aux16m_set_clk()
925 return -ENOENT; in rk3588_aux16m_set_clk()
928 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aux16m_set_clk()
932 rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_0_DIV_MASK, in rk3588_aux16m_set_clk()
933 (div - 1) << CLK_AUX16MHZ_0_DIV_SHIFT); in rk3588_aux16m_set_clk()
936 rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_1_DIV_MASK, in rk3588_aux16m_set_clk()
937 (div - 1) << CLK_AUX16MHZ_1_DIV_SHIFT); in rk3588_aux16m_set_clk()
940 return -ENOENT; in rk3588_aux16m_set_clk()
948 struct rk3588_cru *cru = priv->cru; in rk3588_aclk_vop_get_clk()
949 u32 div, sel, con, parent; in rk3588_aclk_vop_get_clk() local
954 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
955 div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT; in rk3588_aclk_vop_get_clk()
958 parent = priv->gpll_hz; in rk3588_aclk_vop_get_clk()
960 parent = priv->cpll_hz; in rk3588_aclk_vop_get_clk()
962 parent = priv->aupll_hz; in rk3588_aclk_vop_get_clk()
964 parent = priv->npll_hz; in rk3588_aclk_vop_get_clk()
967 return DIV_TO_RATE(parent, div); in rk3588_aclk_vop_get_clk()
969 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
981 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
992 return -ENOENT; in rk3588_aclk_vop_get_clk()
999 struct rk3588_cru *cru = priv->cru; in rk3588_aclk_vop_set_clk()
1000 int src_clk, div; in rk3588_aclk_vop_set_clk() local
1007 div = 1; in rk3588_aclk_vop_set_clk()
1010 div = 2; in rk3588_aclk_vop_set_clk()
1013 div = 1; in rk3588_aclk_vop_set_clk()
1014 } else if (!(priv->cpll_hz % rate)) { in rk3588_aclk_vop_set_clk()
1016 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_aclk_vop_set_clk()
1019 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aclk_vop_set_clk()
1021 rk_clrsetreg(&cru->clksel_con[110], in rk3588_aclk_vop_set_clk()
1025 (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT); in rk3588_aclk_vop_set_clk()
1036 rk_clrsetreg(&cru->clksel_con[110], in rk3588_aclk_vop_set_clk()
1049 rk_clrsetreg(&cru->clksel_con[110], in rk3588_aclk_vop_set_clk()
1054 return -ENOENT; in rk3588_aclk_vop_set_clk()
1062 struct rk3588_cru *cru = priv->cru; in rk3588_dclk_vop_get_clk()
1063 u32 div, sel, con, parent; in rk3588_dclk_vop_get_clk() local
1068 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1069 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1074 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1075 div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1080 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_get_clk()
1081 div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1085 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_get_clk()
1086 div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1090 return -ENOENT; in rk3588_dclk_vop_get_clk()
1094 parent = priv->aupll_hz; in rk3588_dclk_vop_get_clk()
1097 priv->cru, V0PLL); in rk3588_dclk_vop_get_clk()
1099 parent = priv->gpll_hz; in rk3588_dclk_vop_get_clk()
1101 parent = priv->cpll_hz; in rk3588_dclk_vop_get_clk()
1103 return DIV_TO_RATE(parent, div); in rk3588_dclk_vop_get_clk()
1111 struct rk3588_cru *cru = priv->cru; in rk3588_dclk_vop_set_clk()
1113 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3588_dclk_vop_set_clk() local
1120 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1129 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1138 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_set_clk()
1146 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_set_clk()
1153 return -ENOENT; in rk3588_dclk_vop_set_clk()
1158 priv->cru, V0PLL); in rk3588_dclk_vop_set_clk()
1160 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1161 rk_clrsetreg(&cru->clksel_con[conid], in rk3588_dclk_vop_set_clk()
1164 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1166 div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); in rk3588_dclk_vop_set_clk()
1167 rk_clrsetreg(&cru->clksel_con[conid], in rk3588_dclk_vop_set_clk()
1170 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1172 priv->cru, V0PLL, div * rate); in rk3588_dclk_vop_set_clk()
1178 pll_rate = priv->gpll_hz; in rk3588_dclk_vop_set_clk()
1181 pll_rate = priv->cpll_hz; in rk3588_dclk_vop_set_clk()
1184 pll_rate = priv->aupll_hz; in rk3588_dclk_vop_set_clk()
1191 return -EINVAL; in rk3588_dclk_vop_set_clk()
1194 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1195 if (div > 255) in rk3588_dclk_vop_set_clk()
1197 now = pll_rate / div; in rk3588_dclk_vop_set_clk()
1198 if (abs(rate - now) < abs(rate - best_rate)) { in rk3588_dclk_vop_set_clk()
1200 best_div = div; in rk3588_dclk_vop_set_clk()
1203 debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n", in rk3588_dclk_vop_set_clk()
1208 rk_clrsetreg(&cru->clksel_con[conid], in rk3588_dclk_vop_set_clk()
1211 (best_div - 1) << div_shift); in rk3588_dclk_vop_set_clk()
1214 return -EINVAL; in rk3588_dclk_vop_set_clk()
1222 struct rk3588_cru *cru = priv->cru; in rk3588_gmac_get_clk()
1223 u32 con, div; in rk3588_gmac_get_clk() local
1227 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1228 div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1229 return DIV_TO_RATE(priv->cpll_hz, div); in rk3588_gmac_get_clk()
1231 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1232 div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1233 return DIV_TO_RATE(priv->cpll_hz, div); in rk3588_gmac_get_clk()
1235 con = readl(&cru->clksel_con[83]); in rk3588_gmac_get_clk()
1236 div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT; in rk3588_gmac_get_clk()
1237 return DIV_TO_RATE(priv->cpll_hz, div); in rk3588_gmac_get_clk()
1239 con = readl(&cru->clksel_con[84]); in rk3588_gmac_get_clk()
1240 div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT; in rk3588_gmac_get_clk()
1241 return DIV_TO_RATE(priv->cpll_hz, div); in rk3588_gmac_get_clk()
1243 return -ENOENT; in rk3588_gmac_get_clk()
1250 struct rk3588_cru *cru = priv->cru; in rk3588_gmac_set_clk()
1251 int div; in rk3588_gmac_set_clk() local
1253 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_gmac_set_clk()
1257 rk_clrsetreg(&cru->clksel_con[81], in rk3588_gmac_set_clk()
1260 (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT); in rk3588_gmac_set_clk()
1263 rk_clrsetreg(&cru->clksel_con[81], in rk3588_gmac_set_clk()
1266 (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT); in rk3588_gmac_set_clk()
1270 rk_clrsetreg(&cru->clksel_con[83], in rk3588_gmac_set_clk()
1273 (div - 1) << CLK_GMAC_125M_DIV_SHIFT); in rk3588_gmac_set_clk()
1276 rk_clrsetreg(&cru->clksel_con[84], in rk3588_gmac_set_clk()
1279 (div - 1) << CLK_GMAC_50M_DIV_SHIFT); in rk3588_gmac_set_clk()
1282 return -ENOENT; in rk3588_gmac_set_clk()
1290 struct rk3588_cru *cru = priv->cru; in rk3588_uart_get_rate()
1291 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3588_uart_get_rate() local
1323 return -ENOENT; in rk3588_uart_get_rate()
1325 con = readl(&cru->clksel_con[reg + 2]); in rk3588_uart_get_rate()
1327 con = readl(&cru->clksel_con[reg]); in rk3588_uart_get_rate()
1328 div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT; in rk3588_uart_get_rate()
1331 p_rate = priv->gpll_hz; in rk3588_uart_get_rate()
1333 p_rate = priv->cpll_hz; in rk3588_uart_get_rate()
1336 return DIV_TO_RATE(p_rate, div); in rk3588_uart_get_rate()
1338 fracdiv = readl(&cru->clksel_con[reg + 1]); in rk3588_uart_get_rate()
1343 return DIV_TO_RATE(p_rate, div) * n / m; in rk3588_uart_get_rate()
1352 struct rk3588_cru *cru = priv->cru; in rk3588_uart_set_rate()
1353 u32 reg, clk_src, uart_src, div; in rk3588_uart_set_rate() local
1356 if (priv->gpll_hz % rate == 0) { in rk3588_uart_set_rate()
1359 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1360 } else if (priv->cpll_hz % rate == 0) { in rk3588_uart_set_rate()
1363 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1367 div = 2; in rk3588_uart_set_rate()
1371 div = 2; in rk3588_uart_set_rate()
1372 rational_best_approximation(rate, priv->gpll_hz / div, in rk3588_uart_set_rate()
1373 GENMASK(16 - 1, 0), in rk3588_uart_set_rate()
1374 GENMASK(16 - 1, 0), in rk3588_uart_set_rate()
1407 return -ENOENT; in rk3588_uart_set_rate()
1409 rk_clrsetreg(&cru->clksel_con[reg], in rk3588_uart_set_rate()
1413 ((div - 1) << CLK_UART_SRC_DIV_SHIFT)); in rk3588_uart_set_rate()
1414 rk_clrsetreg(&cru->clksel_con[reg + 2], in rk3588_uart_set_rate()
1419 writel(val, &cru->clksel_con[reg + 1]); in rk3588_uart_set_rate()
1427 struct rk3588_cru *cru = priv->cru; in rk3588_pciephy_get_rate()
1428 u32 con, div, src; in rk3588_pciephy_get_rate() local
1432 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1434 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1435 div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1438 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1440 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1441 div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1444 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1446 div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1449 return -ENOENT; in rk3588_pciephy_get_rate()
1453 return DIV_TO_RATE(priv->ppll_hz, div); in rk3588_pciephy_get_rate()
1462 struct rk3588_cru *cru = priv->cru; in rk3588_pciephy_set_rate()
1463 u32 clk_src, div; in rk3588_pciephy_set_rate() local
1467 div = 1; in rk3588_pciephy_set_rate()
1470 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3588_pciephy_set_rate()
1475 rk_clrsetreg(&cru->clksel_con[177], in rk3588_pciephy_set_rate()
1478 rk_clrsetreg(&cru->clksel_con[176], in rk3588_pciephy_set_rate()
1480 ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT)); in rk3588_pciephy_set_rate()
1483 rk_clrsetreg(&cru->clksel_con[177], in rk3588_pciephy_set_rate()
1486 rk_clrsetreg(&cru->clksel_con[176], in rk3588_pciephy_set_rate()
1488 ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT)); in rk3588_pciephy_set_rate()
1491 rk_clrsetreg(&cru->clksel_con[177], in rk3588_pciephy_set_rate()
1495 ((div - 1) << CLK_PCIE_PHY2_PLL_DIV_SHIFT)); in rk3588_pciephy_set_rate()
1498 return -ENOENT; in rk3588_pciephy_set_rate()
1505 static ulong rk3588_clk_get_rate(struct clk *clk) in rk3588_clk_get_rate() argument
1507 struct rk3588_clk_priv *priv = dev_get_priv(clk->dev); in rk3588_clk_get_rate()
1510 if (!priv->gpll_hz) { in rk3588_clk_get_rate()
1511 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rk3588_clk_get_rate()
1512 return -ENOENT; in rk3588_clk_get_rate()
1515 if (!priv->ppll_hz) { in rk3588_clk_get_rate()
1516 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_get_rate()
1517 priv->cru, PPLL); in rk3588_clk_get_rate()
1520 switch (clk->id) { in rk3588_clk_get_rate()
1522 rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru, in rk3588_clk_get_rate()
1526 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru, in rk3588_clk_get_rate()
1530 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru, in rk3588_clk_get_rate()
1534 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1538 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1542 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1546 rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_get_rate()
1550 rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru, in rk3588_clk_get_rate()
1554 rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_get_rate()
1561 rate = rk3588_center_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1566 rate = rk3588_top_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1577 rate = rk3588_i2c_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1584 rate = rk3588_spi_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1590 rate = rk3588_pwm_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1594 rate = rk3588_adc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1601 rate = rk3588_mmc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1609 rk3588_aux16m_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1615 rate = rk3588_aclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1624 rate = rk3588_dclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1630 rate = rk3588_gmac_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1641 rate = rk3588_uart_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1646 rate = rk3588_pciephy_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1650 return -ENOENT; in rk3588_clk_get_rate()
1656 static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) in rk3588_clk_set_rate() argument
1658 struct rk3588_clk_priv *priv = dev_get_priv(clk->dev); in rk3588_clk_set_rate()
1661 if (!priv->gpll_hz) { in rk3588_clk_set_rate()
1662 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rk3588_clk_set_rate()
1663 return -ENOENT; in rk3588_clk_set_rate()
1666 if (!priv->ppll_hz) { in rk3588_clk_set_rate()
1667 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
1668 priv->cru, PPLL); in rk3588_clk_set_rate()
1671 switch (clk->id) { in rk3588_clk_set_rate()
1673 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_set_rate()
1675 priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], in rk3588_clk_set_rate()
1676 priv->cru, CPLL); in rk3588_clk_set_rate()
1679 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_set_rate()
1681 priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], in rk3588_clk_set_rate()
1682 priv->cru, GPLL); in rk3588_clk_set_rate()
1685 ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_set_rate()
1689 ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_set_rate()
1691 priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_clk_set_rate()
1692 priv->cru, V0PLL); in rk3588_clk_set_rate()
1695 ret = rockchip_pll_set_rate(&rk3588_pll_clks[AUPLL], priv->cru, in rk3588_clk_set_rate()
1697 priv->aupll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], in rk3588_clk_set_rate()
1698 priv->cru, AUPLL); in rk3588_clk_set_rate()
1701 ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_set_rate()
1703 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_set_rate()
1704 priv->cru, PPLL); in rk3588_clk_set_rate()
1710 ret = rk3588_center_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1715 ret = rk3588_top_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1726 ret = rk3588_i2c_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1733 ret = rk3588_spi_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1739 ret = rk3588_pwm_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1743 ret = rk3588_adc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1750 ret = rk3588_mmc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1758 rk3588_aux16m_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1764 ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1773 ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1779 ret = rk3588_gmac_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1790 ret = rk3588_uart_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1795 ret = rk3588_pciephy_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1799 return -ENOENT; in rk3588_clk_set_rate()
1812 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1817 int rk3588_mmc_get_phase(struct clk *clk) in rk3588_mmc_get_phase() argument
1819 struct rk3588_clk_priv *priv = dev_get_priv(clk->dev); in rk3588_mmc_get_phase()
1820 struct rk3588_cru *cru = priv->cru; in rk3588_mmc_get_phase()
1825 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_get_phase()
1829 if (clk->id == SCLK_SDMMC_SAMPLE) in rk3588_mmc_get_phase()
1830 raw_value = readl(&cru->sdmmc_con[1]); in rk3588_mmc_get_phase()
1850 int rk3588_mmc_set_phase(struct clk *clk, u32 degrees) in rk3588_mmc_set_phase() argument
1852 struct rk3588_clk_priv *priv = dev_get_priv(clk->dev); in rk3588_mmc_set_phase()
1853 struct rk3588_cru *cru = priv->cru; in rk3588_mmc_set_phase()
1858 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_set_phase()
1867 * don't overflow 32-bit / 64-bit numbers. in rk3588_mmc_set_phase()
1881 if (clk->id == SCLK_SDMMC_SAMPLE) in rk3588_mmc_set_phase()
1882 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk3588_mmc_set_phase()
1885 degrees, delay_num, raw_value, rk3588_mmc_get_phase(clk)); in rk3588_mmc_set_phase()
1890 static int rk3588_clk_get_phase(struct clk *clk) in rk3588_clk_get_phase() argument
1894 debug("%s %ld\n", __func__, clk->id); in rk3588_clk_get_phase()
1895 switch (clk->id) { in rk3588_clk_get_phase()
1897 ret = rk3588_mmc_get_phase(clk); in rk3588_clk_get_phase()
1900 return -ENOENT; in rk3588_clk_get_phase()
1906 static int rk3588_clk_set_phase(struct clk *clk, int degrees) in rk3588_clk_set_phase() argument
1910 debug("%s %ld\n", __func__, clk->id); in rk3588_clk_set_phase()
1911 switch (clk->id) { in rk3588_clk_set_phase()
1913 ret = rk3588_mmc_set_phase(clk, degrees); in rk3588_clk_set_phase()
1916 return -ENOENT; in rk3588_clk_set_phase()
1923 static int __maybe_unused rk3588_dclk_vop_set_parent(struct clk *clk, in rk3588_dclk_vop_set_parent() argument
1924 struct clk *parent) in rk3588_dclk_vop_set_parent()
1926 struct rk3588_clk_priv *priv = dev_get_priv(clk->dev); in rk3588_dclk_vop_set_parent()
1927 struct rk3588_cru *cru = priv->cru; in rk3588_dclk_vop_set_parent()
1929 const char *clock_dev_name = parent->dev->name; in rk3588_dclk_vop_set_parent()
1931 if (parent->id == PLL_V0PLL) in rk3588_dclk_vop_set_parent()
1933 else if (parent->id == PLL_GPLL) in rk3588_dclk_vop_set_parent()
1935 else if (parent->id == PLL_CPLL) in rk3588_dclk_vop_set_parent()
1940 switch (clk->id) { in rk3588_dclk_vop_set_parent()
1942 rk_clrsetreg(&cru->clksel_con[111], DCLK0_VOP_SRC_SEL_MASK, in rk3588_dclk_vop_set_parent()
1946 rk_clrsetreg(&cru->clksel_con[111], DCLK1_VOP_SRC_SEL_MASK, in rk3588_dclk_vop_set_parent()
1950 rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SRC_SEL_MASK, in rk3588_dclk_vop_set_parent()
1954 rk_clrsetreg(&cru->clksel_con[113], DCLK3_VOP_SRC_SEL_MASK, in rk3588_dclk_vop_set_parent()
1964 rk_clrsetreg(&cru->clksel_con[112], DCLK0_VOP_SEL_MASK, in rk3588_dclk_vop_set_parent()
1974 rk_clrsetreg(&cru->clksel_con[112], DCLK1_VOP_SEL_MASK, in rk3588_dclk_vop_set_parent()
1984 rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SEL_MASK, in rk3588_dclk_vop_set_parent()
1988 return -EINVAL; in rk3588_dclk_vop_set_parent()
1993 static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent) in rk3588_clk_set_parent() argument
1995 switch (clk->id) { in rk3588_clk_set_parent()
2003 return rk3588_dclk_vop_set_parent(clk, parent); in rk3588_clk_set_parent()
2005 return -ENOENT; in rk3588_clk_set_parent()
2024 int ret, div; in rk3588_clk_init() local
2026 div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz); in rk3588_clk_init()
2027 rk_clrsetreg(&priv->cru->clksel_con[38], in rk3588_clk_init()
2030 div << ACLK_BUS_ROOT_DIV_SHIFT); in rk3588_clk_init()
2032 if (priv->cpll_hz != CPLL_HZ) { in rk3588_clk_init()
2033 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_init()
2036 priv->cpll_hz = CPLL_HZ; in rk3588_clk_init()
2038 if (priv->gpll_hz != GPLL_HZ) { in rk3588_clk_init()
2039 ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_init()
2042 priv->gpll_hz = GPLL_HZ; in rk3588_clk_init()
2046 if (priv->ppll_hz != PPLL_HZ) { in rk3588_clk_init()
2047 ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_init()
2049 priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], in rk3588_clk_init()
2050 priv->cru, PPLL); in rk3588_clk_init()
2053 rk_clrsetreg(&priv->cru->clksel_con[9], in rk3588_clk_init()
2064 struct clk clk; in rk3588_clk_probe() local
2066 priv->sync_kernel = false; in rk3588_clk_probe()
2069 rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru, in rk3588_clk_probe()
2071 rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru, in rk3588_clk_probe()
2073 if (!priv->armclk_enter_hz) { in rk3588_clk_probe()
2074 ret = rockchip_pll_set_rate(&rk3588_pll_clks[LPLL], priv->cru, in rk3588_clk_probe()
2076 priv->armclk_enter_hz = in rk3588_clk_probe()
2078 priv->cru, LPLL); in rk3588_clk_probe()
2079 priv->armclk_init_hz = priv->armclk_enter_hz; in rk3588_clk_probe()
2083 ret = rockchip_get_scmi_clk(&clk.dev); in rk3588_clk_probe()
2085 printf("Failed to get scmi clk dev\n"); in rk3588_clk_probe()
2088 clk.id = SCMI_SPLL; in rk3588_clk_probe()
2089 ret = clk_set_rate(&clk, 702000000); in rk3588_clk_probe()
2095 if (!priv->armclk_enter_hz) { in rk3588_clk_probe()
2096 clk.id = SCMI_CLK_CPUL; in rk3588_clk_probe()
2097 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); in rk3588_clk_probe()
2101 priv->armclk_enter_hz = CPU_PVTPLL_HZ; in rk3588_clk_probe()
2102 priv->armclk_init_hz = CPU_PVTPLL_HZ; in rk3588_clk_probe()
2105 clk.id = SCMI_CLK_CPUB01; in rk3588_clk_probe()
2106 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); in rk3588_clk_probe()
2109 clk.id = SCMI_CLK_CPUB23; in rk3588_clk_probe()
2110 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); in rk3588_clk_probe()
2115 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3588_clk_probe()
2116 if (IS_ERR(priv->grf)) in rk3588_clk_probe()
2117 return PTR_ERR(priv->grf); in rk3588_clk_probe()
2121 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk3588_clk_probe()
2126 priv->sync_kernel = true; in rk3588_clk_probe()
2135 priv->cru = dev_read_addr_ptr(dev); in rk3588_clk_ofdata_to_platdata()
2154 priv->glb_srst_fst_value = offsetof(struct rk3588_cru, in rk3588_clk_bind()
2156 priv->glb_srst_snd_value = offsetof(struct rk3588_cru, in rk3588_clk_bind()
2158 sys_child->priv = priv; in rk3588_clk_bind()
2167 sf_priv->sf_reset_offset = offsetof(struct rk3588_cru, in rk3588_clk_bind()
2169 sf_priv->sf_reset_num = 49158; in rk3588_clk_bind()
2170 sf_child->priv = sf_priv; in rk3588_clk_bind()
2177 { .compatible = "rockchip,rk3588-cru" },
2203 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
2204 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
2206 static ulong rk3588_clk_scmi_get_rate(struct clk *clk) in rk3588_clk_scmi_get_rate() argument
2208 u32 src, div; in rk3588_clk_scmi_get_rate() local
2210 switch (clk->id) { in rk3588_clk_scmi_get_rate()
2222 div = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x0fc0; in rk3588_clk_scmi_get_rate()
2223 div = div >> 6; in rk3588_clk_scmi_get_rate()
2225 return SPLL_RATE / (div + 1); in rk3588_clk_scmi_get_rate()
2227 return OSC_HZ / (div + 1); in rk3588_clk_scmi_get_rate()
2229 return GPLL_RATE / (div + 1); in rk3588_clk_scmi_get_rate()
2232 div = readl(SCRU_BASE + RK3588_CLKSEL_CON(3)) & 0x001f; in rk3588_clk_scmi_get_rate()
2234 return SPLL_RATE / (div + 1); in rk3588_clk_scmi_get_rate()
2236 return GPLL_RATE / (div + 1); in rk3588_clk_scmi_get_rate()
2307 return -ENOENT; in rk3588_clk_scmi_get_rate()
2311 static ulong rk3588_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3588_clk_scmi_set_rate() argument
2313 u32 src, div; in rk3588_clk_scmi_set_rate() local
2324 switch (clk->id) { in rk3588_clk_scmi_set_rate()
2339 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_clk_scmi_set_rate()
2340 writel(CLKDIV_6BITS_SHF(div - 1, 6) | in rk3588_clk_scmi_set_rate()
2344 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2345 writel(CLKDIV_6BITS_SHF(div - 1, 6) | in rk3588_clk_scmi_set_rate()
2349 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2350 writel(CLKDIV_6BITS_SHF(div - 1, 6) | in rk3588_clk_scmi_set_rate()
2357 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2358 writel(CLKDIV_5BITS_SHF(div - 1, 0) | in rk3588_clk_scmi_set_rate()
2362 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2363 writel(CLKDIV_5BITS_SHF(div - 1, 0) | in rk3588_clk_scmi_set_rate()
2449 return -ENOENT; in rk3588_clk_scmi_set_rate()
2469 * soc_clk_dump() - Print clock frequencies
2472 * Implementation for the clk dump command.
2479 struct clk clk; in soc_clk_dump() local
2493 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
2494 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
2495 priv->armclk_enter_hz / 1000, in soc_clk_dump()
2496 priv->armclk_init_hz / 1000, in soc_clk_dump()
2497 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
2498 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
2501 if (clk_dump->name) { in soc_clk_dump()
2502 memset(&clk, 0, sizeof(struct clk)); in soc_clk_dump()
2503 clk.id = clk_dump->id; in soc_clk_dump()
2504 if (clk_dump->is_cru) in soc_clk_dump()
2505 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
2509 rate = clk_get_rate(&clk); in soc_clk_dump()
2510 clk_free(&clk); in soc_clk_dump()
2512 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
2515 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()