22 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
285 	u32 con, sel, div, rate, prate;  in rk3588_top_get_clk()  local
655 	u32 div, sel, con, prate;  in rk3588_adc_get_clk()  local
746 	u32 sel, con, div, prate;  in rk3588_mmc_get_clk()  local
814 	int src_clk, div;  in rk3588_mmc_set_clk()  local
900 	u32 div, con, parent;  in rk3588_aux16m_get_clk()  local
921 	u32 div;  in rk3588_aux16m_set_clk()  local
949 	u32 div, sel, con, parent;  in rk3588_aclk_vop_get_clk()  local
1000 	int src_clk, div;  in rk3588_aclk_vop_set_clk()  local
1063 	u32 div, sel, con, parent;  in rk3588_dclk_vop_get_clk()  local
1113 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3588_dclk_vop_set_clk()  local
1223 	u32 con, div;  in rk3588_gmac_get_clk()  local
1251 	int div;  in rk3588_gmac_set_clk()  local
1291 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3588_uart_get_rate()  local
1353 	u32 reg, clk_src, uart_src, div;  in rk3588_uart_set_rate()  local
1428 	u32 con, div, src;  in rk3588_pciephy_get_rate()  local
1463 	u32 clk_src, div;  in rk3588_pciephy_set_rate()  local
2024 	int ret, div;  in rk3588_clk_init()  local
2203 #define CLKDIV_6BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x3fU, shift)  argument
2204 #define CLKDIV_5BITS_SHF(div, shift)	BITS_WITH_WMASK(div, 0x1fU, shift)  argument
2208 	u32 src, div;  in rk3588_clk_scmi_get_rate()  local
2313 	u32 src, div;  in rk3588_clk_scmi_set_rate()  local