Lines Matching refs:src_clk
771 int src_clk; in rk3568_bus_set_clk() local
776 src_clk = ACLK_BUS_SEL_200M; in rk3568_bus_set_clk()
778 src_clk = ACLK_BUS_SEL_150M; in rk3568_bus_set_clk()
780 src_clk = ACLK_BUS_SEL_100M; in rk3568_bus_set_clk()
782 src_clk = ACLK_BUS_SEL_24M; in rk3568_bus_set_clk()
785 src_clk << ACLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
790 src_clk = PCLK_BUS_SEL_100M; in rk3568_bus_set_clk()
792 src_clk = PCLK_BUS_SEL_75M; in rk3568_bus_set_clk()
794 src_clk = PCLK_BUS_SEL_50M; in rk3568_bus_set_clk()
796 src_clk = PCLK_BUS_SEL_24M; in rk3568_bus_set_clk()
799 src_clk << PCLK_BUS_SEL_SHIFT); in rk3568_bus_set_clk()
851 int src_clk; in rk3568_perimid_set_clk() local
856 src_clk = ACLK_PERIMID_SEL_300M; in rk3568_perimid_set_clk()
858 src_clk = ACLK_PERIMID_SEL_200M; in rk3568_perimid_set_clk()
860 src_clk = ACLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
862 src_clk = ACLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
865 src_clk << ACLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
869 src_clk = HCLK_PERIMID_SEL_150M; in rk3568_perimid_set_clk()
871 src_clk = HCLK_PERIMID_SEL_100M; in rk3568_perimid_set_clk()
873 src_clk = HCLK_PERIMID_SEL_75M; in rk3568_perimid_set_clk()
875 src_clk = HCLK_PERIMID_SEL_24M; in rk3568_perimid_set_clk()
878 src_clk << HCLK_PERIMID_SEL_SHIFT); in rk3568_perimid_set_clk()
954 int src_clk; in rk3568_top_set_clk() local
959 src_clk = ACLK_TOP_HIGH_SEL_500M; in rk3568_top_set_clk()
961 src_clk = ACLK_TOP_HIGH_SEL_400M; in rk3568_top_set_clk()
963 src_clk = ACLK_TOP_HIGH_SEL_300M; in rk3568_top_set_clk()
965 src_clk = ACLK_TOP_HIGH_SEL_24M; in rk3568_top_set_clk()
968 src_clk << ACLK_TOP_HIGH_SEL_SHIFT); in rk3568_top_set_clk()
972 src_clk = ACLK_TOP_LOW_SEL_400M; in rk3568_top_set_clk()
974 src_clk = ACLK_TOP_LOW_SEL_300M; in rk3568_top_set_clk()
976 src_clk = ACLK_TOP_LOW_SEL_200M; in rk3568_top_set_clk()
978 src_clk = ACLK_TOP_LOW_SEL_24M; in rk3568_top_set_clk()
981 src_clk << ACLK_TOP_LOW_SEL_SHIFT); in rk3568_top_set_clk()
985 src_clk = HCLK_TOP_SEL_150M; in rk3568_top_set_clk()
987 src_clk = HCLK_TOP_SEL_100M; in rk3568_top_set_clk()
989 src_clk = HCLK_TOP_SEL_75M; in rk3568_top_set_clk()
991 src_clk = HCLK_TOP_SEL_24M; in rk3568_top_set_clk()
994 src_clk << HCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
998 src_clk = PCLK_TOP_SEL_100M; in rk3568_top_set_clk()
1000 src_clk = PCLK_TOP_SEL_75M; in rk3568_top_set_clk()
1002 src_clk = PCLK_TOP_SEL_50M; in rk3568_top_set_clk()
1004 src_clk = PCLK_TOP_SEL_24M; in rk3568_top_set_clk()
1007 src_clk << PCLK_TOP_SEL_SHIFT); in rk3568_top_set_clk()
1052 int src_clk; in rk3568_i2c_set_clk() local
1055 src_clk = CLK_I2C_SEL_200M; in rk3568_i2c_set_clk()
1057 src_clk = CLK_I2C_SEL_100M; in rk3568_i2c_set_clk()
1059 src_clk = CLK_I2C_SEL_24M; in rk3568_i2c_set_clk()
1068 src_clk << CLK_I2C_SEL_SHIFT); in rk3568_i2c_set_clk()
1117 int src_clk; in rk3568_spi_set_clk() local
1120 src_clk = CLK_SPI_SEL_200M; in rk3568_spi_set_clk()
1122 src_clk = CLK_SPI_SEL_CPLL_100M; in rk3568_spi_set_clk()
1124 src_clk = CLK_SPI_SEL_24M; in rk3568_spi_set_clk()
1130 src_clk << CLK_SPI0_SEL_SHIFT); in rk3568_spi_set_clk()
1135 src_clk << CLK_SPI1_SEL_SHIFT); in rk3568_spi_set_clk()
1140 src_clk << CLK_SPI2_SEL_SHIFT); in rk3568_spi_set_clk()
1145 src_clk << CLK_SPI3_SEL_SHIFT); in rk3568_spi_set_clk()
1191 int src_clk; in rk3568_pwm_set_clk() local
1194 src_clk = CLK_PWM_SEL_100M; in rk3568_pwm_set_clk()
1196 src_clk = CLK_PWM_SEL_24M; in rk3568_pwm_set_clk()
1202 src_clk << CLK_PWM1_SEL_SHIFT); in rk3568_pwm_set_clk()
1207 src_clk << CLK_PWM2_SEL_SHIFT); in rk3568_pwm_set_clk()
1212 src_clk << CLK_PWM3_SEL_SHIFT); in rk3568_pwm_set_clk()
1359 u32 src_clk, mask, shift; in rk3568_crypto_set_rate() local
1367 src_clk = ACLK_SECURE_FLASH_SEL_200M; in rk3568_crypto_set_rate()
1369 src_clk = ACLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1371 src_clk = ACLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1373 src_clk = ACLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1381 src_clk = HCLK_SECURE_FLASH_SEL_150M; in rk3568_crypto_set_rate()
1383 src_clk = HCLK_SECURE_FLASH_SEL_100M; in rk3568_crypto_set_rate()
1385 src_clk = HCLK_SECURE_FLASH_SEL_75M; in rk3568_crypto_set_rate()
1387 src_clk = HCLK_SECURE_FLASH_SEL_24M; in rk3568_crypto_set_rate()
1393 src_clk = CLK_CRYPTO_CORE_SEL_200M; in rk3568_crypto_set_rate()
1395 src_clk = CLK_CRYPTO_CORE_SEL_150M; in rk3568_crypto_set_rate()
1397 src_clk = CLK_CRYPTO_CORE_SEL_100M; in rk3568_crypto_set_rate()
1403 src_clk = CLK_CRYPTO_PKA_SEL_300M; in rk3568_crypto_set_rate()
1405 src_clk = CLK_CRYPTO_PKA_SEL_200M; in rk3568_crypto_set_rate()
1407 src_clk = CLK_CRYPTO_PKA_SEL_100M; in rk3568_crypto_set_rate()
1413 rk_clrsetreg(&cru->clksel_con[27], mask, src_clk << shift); in rk3568_crypto_set_rate()
1463 int src_clk; in rk3568_sdmmc_set_clk() local
1468 src_clk = CLK_SDMMC_SEL_24M; in rk3568_sdmmc_set_clk()
1471 src_clk = CLK_SDMMC_SEL_400M; in rk3568_sdmmc_set_clk()
1474 src_clk = CLK_SDMMC_SEL_300M; in rk3568_sdmmc_set_clk()
1477 src_clk = CLK_SDMMC_SEL_100M; in rk3568_sdmmc_set_clk()
1481 src_clk = CLK_SDMMC_SEL_50M; in rk3568_sdmmc_set_clk()
1485 src_clk = CLK_SDMMC_SEL_750K; in rk3568_sdmmc_set_clk()
1496 src_clk << CLK_SDMMC0_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1501 src_clk << CLK_SDMMC1_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1506 src_clk << CLK_SDMMC2_SEL_SHIFT); in rk3568_sdmmc_set_clk()
1543 int src_clk; in rk3568_sfc_set_clk() local
1547 src_clk = SCLK_SFC_SEL_24M; in rk3568_sfc_set_clk()
1550 src_clk = SCLK_SFC_SEL_50M; in rk3568_sfc_set_clk()
1553 src_clk = SCLK_SFC_SEL_75M; in rk3568_sfc_set_clk()
1556 src_clk = SCLK_SFC_SEL_100M; in rk3568_sfc_set_clk()
1559 src_clk = SCLK_SFC_SEL_125M; in rk3568_sfc_set_clk()
1562 src_clk = SCLK_SFC_SEL_150M; in rk3568_sfc_set_clk()
1570 src_clk << SCLK_SFC_SEL_SHIFT); in rk3568_sfc_set_clk()
1599 int src_clk; in rk3568_nand_set_clk() local
1603 src_clk = NCLK_NANDC_SEL_24M; in rk3568_nand_set_clk()
1606 src_clk = NCLK_NANDC_SEL_100M; in rk3568_nand_set_clk()
1609 src_clk = NCLK_NANDC_SEL_150M; in rk3568_nand_set_clk()
1612 src_clk = NCLK_NANDC_SEL_200M; in rk3568_nand_set_clk()
1620 src_clk << NCLK_NANDC_SEL_SHIFT); in rk3568_nand_set_clk()
1653 int src_clk; in rk3568_emmc_set_clk() local
1657 src_clk = CCLK_EMMC_SEL_24M; in rk3568_emmc_set_clk()
1661 src_clk = CCLK_EMMC_SEL_50M; in rk3568_emmc_set_clk()
1664 src_clk = CCLK_EMMC_SEL_100M; in rk3568_emmc_set_clk()
1667 src_clk = CCLK_EMMC_SEL_150M; in rk3568_emmc_set_clk()
1670 src_clk = CCLK_EMMC_SEL_200M; in rk3568_emmc_set_clk()
1674 src_clk = CCLK_EMMC_SEL_375K; in rk3568_emmc_set_clk()
1682 src_clk << CCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_clk()
1709 int src_clk; in rk3568_emmc_set_bclk() local
1713 src_clk = BCLK_EMMC_SEL_200M; in rk3568_emmc_set_bclk()
1716 src_clk = BCLK_EMMC_SEL_150M; in rk3568_emmc_set_bclk()
1719 src_clk = BCLK_EMMC_SEL_125M; in rk3568_emmc_set_bclk()
1727 src_clk << BCLK_EMMC_SEL_SHIFT); in rk3568_emmc_set_bclk()
1919 int src_clk; in rk3568_gmac_src_set_clk() local
1923 src_clk = CLK_MAC0_2TOP_SEL_125M; in rk3568_gmac_src_set_clk()
1926 src_clk = CLK_MAC0_2TOP_SEL_50M; in rk3568_gmac_src_set_clk()
1929 src_clk = CLK_MAC0_2TOP_SEL_25M; in rk3568_gmac_src_set_clk()
1937 src_clk << CLK_MAC0_2TOP_SEL_SHIFT); in rk3568_gmac_src_set_clk()
1969 int src_clk; in rk3568_gmac_out_set_clk() local
1973 src_clk = CLK_MAC0_OUT_SEL_125M; in rk3568_gmac_out_set_clk()
1976 src_clk = CLK_MAC0_OUT_SEL_50M; in rk3568_gmac_out_set_clk()
1979 src_clk = CLK_MAC0_OUT_SEL_25M; in rk3568_gmac_out_set_clk()
1982 src_clk = CLK_MAC0_OUT_SEL_24M; in rk3568_gmac_out_set_clk()
1990 src_clk << CLK_MAC0_OUT_SEL_SHIFT); in rk3568_gmac_out_set_clk()
2022 int src_clk; in rk3568_gmac_ptp_ref_set_clk() local
2026 src_clk = CLK_GMAC0_PTP_REF_SEL_62_5M; in rk3568_gmac_ptp_ref_set_clk()
2029 src_clk = CLK_GMAC0_PTP_REF_SEL_100M; in rk3568_gmac_ptp_ref_set_clk()
2032 src_clk = CLK_GMAC0_PTP_REF_SEL_50M; in rk3568_gmac_ptp_ref_set_clk()
2035 src_clk = CLK_GMAC0_PTP_REF_SEL_24M; in rk3568_gmac_ptp_ref_set_clk()
2043 src_clk << CLK_GMAC0_PTP_REF_SEL_SHIFT); in rk3568_gmac_ptp_ref_set_clk()