1742 		parent = priv->gpll_hz;  in rk3568_aclk_vop_get_clk()
1762 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_aclk_vop_set_clk()
1802 		parent = priv->gpll_hz;  in rk3568_dclk_vop_get_clk()
1856 				pll_rate = priv->gpll_hz;  in rk3568_dclk_vop_set_clk()
2134 			p_rate = priv->gpll_hz;  in rk3568_rkvdec_get_clk()
2149 			p_rate = priv->gpll_hz;  in rk3568_rkvdec_get_clk()
2170 			p_rate = priv->gpll_hz;  in rk3568_rkvdec_set_clk()
2189 			p_rate = priv->gpll_hz;  in rk3568_rkvdec_set_clk()
2247 		p_rate = priv->gpll_hz;  in rk3568_uart_get_rate()
2273 	if (priv->gpll_hz % rate == 0) {  in rk3568_uart_set_rate()
2276 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_uart_set_rate()
2280 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_uart_set_rate()
2289 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3568_uart_set_rate()
2391 		p_rate = priv->gpll_hz;  in rk3568_i2s3_get_rate()
2418 	if (priv->gpll_hz % rate == 0) {  in rk3568_i2s3_set_rate()
2421 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_i2s3_set_rate()
2425 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3568_i2s3_set_rate()
2434 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3568_i2s3_set_rate()
2508 	if (!priv->gpll_hz) {  in rk3568_clk_get_rate()
2509 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);  in rk3568_clk_get_rate()
2690 	if (!priv->gpll_hz) {  in rk3568_clk_set_rate()
2691 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);  in rk3568_clk_set_rate()
2711 		priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL],  in rk3568_clk_set_rate()
3254 	if (priv->gpll_hz != GPLL_HZ) {  in rk3568_clk_init()
3258 			priv->gpll_hz = GPLL_HZ;  in rk3568_clk_init()