668 	return DIV_TO_RATE(priv->cpll_hz, div);  in rk3568_cpll_div_get_rate()
722 	div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3568_cpll_div_set_rate()
1744 		parent = priv->cpll_hz;  in rk3568_aclk_vop_get_clk()
1758 	if ((priv->cpll_hz % rate) == 0) {  in rk3568_aclk_vop_set_clk()
1759 		src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3568_aclk_vop_set_clk()
1804 		parent = priv->cpll_hz;  in rk3568_dclk_vop_get_clk()
1859 				pll_rate = priv->cpll_hz;  in rk3568_dclk_vop_set_clk()
2087 	p_rate = DIV_TO_RATE(priv->cpll_hz, div);  in rk3568_ebc_get_clk()
2108 	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3568_ebc_set_clk()
2132 			p_rate = priv->cpll_hz;  in rk3568_rkvdec_get_clk()
2143 			p_rate = priv->cpll_hz;  in rk3568_rkvdec_get_clk()
2168 			p_rate = priv->cpll_hz;  in rk3568_rkvdec_set_clk()
2183 			p_rate = priv->cpll_hz;  in rk3568_rkvdec_set_clk()
2249 		p_rate = priv->cpll_hz;  in rk3568_uart_get_rate()
2277 	} else if (priv->cpll_hz % rate == 0) {  in rk3568_uart_set_rate()
2393 		p_rate = priv->cpll_hz;  in rk3568_i2s3_get_rate()
2422 	} else if (priv->cpll_hz % rate == 0) {  in rk3568_i2s3_set_rate()
2705 		priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL],  in rk3568_clk_set_rate()
3248 	if (priv->cpll_hz != CPLL_HZ) {  in rk3568_clk_init()
3252 			priv->cpll_hz = CPLL_HZ;  in rk3568_clk_init()