248 	u32 div, con;  in rk3568_i2c_get_pmuclk()  local
252 		con = readl(&pmucru->pmu_clksel_con[3]);  in rk3568_i2c_get_pmuclk()
253 		div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT;  in rk3568_i2c_get_pmuclk()
287 	u32 div, sel, con, parent;  in rk3568_pwm_get_pmuclk()  local
291 		con = readl(&pmucru->pmu_clksel_con[6]);  in rk3568_pwm_get_pmuclk()
292 		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;  in rk3568_pwm_get_pmuclk()
293 		div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT;  in rk3568_pwm_get_pmuclk()
339 	u32 div, con, sel, parent;  in rk3568_pmu_get_pmuclk()  local
341 	con = readl(&pmucru->pmu_clksel_con[2]);  in rk3568_pmu_get_pmuclk()
342 	sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;  in rk3568_pmu_get_pmuclk()
343 	div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT;  in rk3568_pmu_get_pmuclk()
620 	int div, mask, shift, con;  in rk3568_cpll_div_get_rate()  local
624 		con = 78;  in rk3568_cpll_div_get_rate()
629 		con = 79;  in rk3568_cpll_div_get_rate()
634 		con = 79;  in rk3568_cpll_div_get_rate()
639 		con = 80;  in rk3568_cpll_div_get_rate()
644 		con = 82;  in rk3568_cpll_div_get_rate()
649 		con = 80;  in rk3568_cpll_div_get_rate()
654 		con = 81;  in rk3568_cpll_div_get_rate()
659 		con = 81;  in rk3568_cpll_div_get_rate()
667 	div = (readl(&cru->clksel_con[con]) & mask) >> shift;  in rk3568_cpll_div_get_rate()
675 	int div, mask, shift, con;  in rk3568_cpll_div_set_rate()  local
679 		con = 78;  in rk3568_cpll_div_set_rate()
684 		con = 79;  in rk3568_cpll_div_set_rate()
689 		con = 79;  in rk3568_cpll_div_set_rate()
694 		con = 80;  in rk3568_cpll_div_set_rate()
699 		con = 82;  in rk3568_cpll_div_set_rate()
704 		con = 80;  in rk3568_cpll_div_set_rate()
709 		con = 81;  in rk3568_cpll_div_set_rate()
714 		con = 81;  in rk3568_cpll_div_set_rate()
724 	rk_clrsetreg(&cru->clksel_con[con],  in rk3568_cpll_div_set_rate()
732 	u32 con, sel, rate;  in rk3568_bus_get_clk()  local
736 		con = readl(&cru->clksel_con[50]);  in rk3568_bus_get_clk()
737 		sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
749 		con = readl(&cru->clksel_con[50]);  in rk3568_bus_get_clk()
750 		sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
813 	u32 con, sel, rate;  in rk3568_perimid_get_clk()  local
817 		con = readl(&cru->clksel_con[10]);  in rk3568_perimid_get_clk()
818 		sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
829 		con = readl(&cru->clksel_con[10]);  in rk3568_perimid_get_clk()
830 		sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
892 	u32 con, sel, rate;  in rk3568_top_get_clk()  local
896 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
897 		sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT;  in rk3568_top_get_clk()
908 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
909 		sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT;  in rk3568_top_get_clk()
920 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
921 		sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
932 		con = readl(&cru->clksel_con[73]);  in rk3568_top_get_clk()
933 		sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
1021 	u32 sel, con;  in rk3568_i2c_get_clk()  local
1030 		con = readl(&cru->clksel_con[71]);  in rk3568_i2c_get_clk()
1031 		sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;  in rk3568_i2c_get_clk()
1080 	u32 sel, con;  in rk3568_spi_get_clk()  local
1082 	con = readl(&cru->clksel_con[72]);  in rk3568_spi_get_clk()
1086 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rk3568_spi_get_clk()
1089 		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;  in rk3568_spi_get_clk()
1092 		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;  in rk3568_spi_get_clk()
1095 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;  in rk3568_spi_get_clk()
1157 	u32 sel, con;  in rk3568_pwm_get_clk()  local
1159 	con = readl(&cru->clksel_con[72]);  in rk3568_pwm_get_clk()
1163 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rk3568_pwm_get_clk()
1166 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rk3568_pwm_get_clk()
1169 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;  in rk3568_pwm_get_clk()
1224 	u32 div, sel, con, prate;  in rk3568_adc_get_clk()  local
1230 		con = readl(&cru->clksel_con[51]);  in rk3568_adc_get_clk()
1231 		div = (con & CLK_TSADC_TSEN_DIV_MASK) >>  in rk3568_adc_get_clk()
1233 		sel = (con & CLK_TSADC_TSEN_SEL_MASK) >>  in rk3568_adc_get_clk()
1241 		con = readl(&cru->clksel_con[51]);  in rk3568_adc_get_clk()
1242 		div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;  in rk3568_adc_get_clk()
1300 	u32 sel, con;  in rk3568_crypto_get_rate()  local
1305 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1306 		sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1319 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1320 		sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1331 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1332 		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >>  in rk3568_crypto_get_rate()
1341 		con = readl(&cru->clksel_con[27]);  in rk3568_crypto_get_rate()
1342 		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >>  in rk3568_crypto_get_rate()
1421 	u32 sel, con;  in rk3568_sdmmc_get_clk()  local
1426 		con = readl(&cru->clksel_con[30]);  in rk3568_sdmmc_get_clk()
1427 		sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1430 		con = readl(&cru->clksel_con[30]);  in rk3568_sdmmc_get_clk()
1431 		sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1434 		con = readl(&cru->clksel_con[32]);  in rk3568_sdmmc_get_clk()
1435 		sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1518 	u32 sel, con;  in rk3568_sfc_get_clk()  local
1520 	con = readl(&cru->clksel_con[28]);  in rk3568_sfc_get_clk()
1521 	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;  in rk3568_sfc_get_clk()
1578 	u32 sel, con;  in rk3568_nand_get_clk()  local
1580 	con = readl(&cru->clksel_con[28]);  in rk3568_nand_get_clk()
1581 	sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT;  in rk3568_nand_get_clk()
1628 	u32 sel, con;  in rk3568_emmc_get_clk()  local
1630 	con = readl(&cru->clksel_con[28]);  in rk3568_emmc_get_clk()
1631 	sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_clk()
1690 	u32 sel, con;  in rk3568_emmc_get_bclk()  local
1692 	con = readl(&cru->clksel_con[28]);  in rk3568_emmc_get_bclk()
1693 	sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_bclk()
1736 	u32 div, sel, con, parent;  in rk3568_aclk_vop_get_clk()  local
1738 	con = readl(&cru->clksel_con[38]);  in rk3568_aclk_vop_get_clk()
1739 	div = (con & ACLK_VOP_PRE_DIV_MASK) >> ACLK_VOP_PRE_DIV_SHIFT;  in rk3568_aclk_vop_get_clk()
1740 	sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT;  in rk3568_aclk_vop_get_clk()
1777 	u32 conid, div, sel, con, parent;  in rk3568_dclk_vop_get_clk()  local
1793 	con = readl(&cru->clksel_con[conid]);  in rk3568_dclk_vop_get_clk()
1794 	div = (con & DCLK0_VOP_DIV_MASK) >> DCLK0_VOP_DIV_SHIFT;  in rk3568_dclk_vop_get_clk()
1795 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_get_clk()
1818 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3568_dclk_vop_set_clk()  local
1834 	con = readl(&cru->clksel_con[conid]);  in rk3568_dclk_vop_set_clk()
1835 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_set_clk()
1896 	u32 sel, con;  in rk3568_gmac_src_get_clk()  local
1898 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_src_get_clk()
1899 	sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT;  in rk3568_gmac_src_get_clk()
1946 	u32 sel, con;  in rk3568_gmac_out_get_clk()  local
1948 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_out_get_clk()
1949 	sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT;  in rk3568_gmac_out_get_clk()
1999 	u32 sel, con;  in rk3568_gmac_ptp_ref_get_clk()  local
2001 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_ptp_ref_get_clk()
2002 	sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT;  in rk3568_gmac_ptp_ref_get_clk()
2052 	u32 con, sel, div_sel;  in rk3568_gmac_tx_rx_set_clk()  local
2054 	con = readl(&cru->clksel_con[31 + mac_id * 2]);  in rk3568_gmac_tx_rx_set_clk()
2055 	sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT;  in rk3568_gmac_tx_rx_set_clk()
2083 	u32 con, div, p_rate;  in rk3568_ebc_get_clk()  local
2085 	con = readl(&cru->clksel_con[79]);  in rk3568_ebc_get_clk()
2086 	div = (con & CPLL_333M_DIV_MASK) >> CPLL_333M_DIV_SHIFT;  in rk3568_ebc_get_clk()
2089 	con = readl(&cru->clksel_con[43]);  in rk3568_ebc_get_clk()
2090 	div = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;  in rk3568_ebc_get_clk()
2123 	u32 con, div, src, p_rate;  in rk3568_rkvdec_get_clk()  local
2128 		con = readl(&cru->clksel_con[47]);  in rk3568_rkvdec_get_clk()
2129 		src = (con & ACLK_RKVDEC_SEL_MASK) >> ACLK_RKVDEC_SEL_SHIFT;  in rk3568_rkvdec_get_clk()
2130 		div = (con & ACLK_RKVDEC_DIV_MASK) >> ACLK_RKVDEC_DIV_SHIFT;  in rk3568_rkvdec_get_clk()
2137 		con = readl(&cru->clksel_con[49]);  in rk3568_rkvdec_get_clk()
2138 		src = (con & CLK_RKVDEC_CORE_SEL_MASK)  in rk3568_rkvdec_get_clk()
2140 		div = (con & CLK_RKVDEC_CORE_DIV_MASK)  in rk3568_rkvdec_get_clk()
2208 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3568_uart_get_rate()  local
2242 	con = readl(&cru->clksel_con[reg]);  in rk3568_uart_get_rate()
2243 	src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;  in rk3568_uart_get_rate()
2244 	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;  in rk3568_uart_get_rate()
2245 	p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;  in rk3568_uart_get_rate()
2344 	u32 con, div, src, p_rate;  in rk3568_i2s3_get_rate()  local
2350 		con = readl(&cru->clksel_con[21]);  in rk3568_i2s3_get_rate()
2351 		src = (con & I2S3_MCLKOUT_TX_SEL_MASK) >>  in rk3568_i2s3_get_rate()
2359 		con = readl(&cru->clksel_con[83]);  in rk3568_i2s3_get_rate()
2360 		src = (con & I2S3_MCLKOUT_TX_SEL_MASK) >>  in rk3568_i2s3_get_rate()
2368 		con = readl(&grf->soc_con2);  in rk3568_i2s3_get_rate()
2369 		src = (con & I2S3_MCLKOUT_SEL_MASK)  in rk3568_i2s3_get_rate()
2386 	con = readl(&cru->clksel_con[reg]);  in rk3568_i2s3_get_rate()
2387 	src = (con & CLK_I2S3_SEL_MASK) >> CLK_I2S3_SEL_SHIFT;  in rk3568_i2s3_get_rate()
2388 	div = (con & CLK_I2S3_SRC_DIV_MASK) >> CLK_I2S3_SRC_DIV_SHIFT;  in rk3568_i2s3_get_rate()
2389 	p_src = (con & CLK_I2S3_SRC_SEL_MASK) >> CLK_I2S3_SRC_SEL_SHIFT;  in rk3568_i2s3_get_rate()
2415 	u32 reg, con, clk_src, i2s_src, div;  in rk3568_i2s3_set_rate()  local
2470 		con = readl(&grf->soc_con2);  in rk3568_i2s3_set_rate()
2471 		clk_src = (con & I2S3_MCLKOUT_SEL_MASK)  in rk3568_i2s3_set_rate()