clk/rockchip/clk_rk3568.c

82 	[HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
386 		rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],  in rk3568_pmuclk_get_rate()
387 					     priv->pmucru, HPLL);  in rk3568_pmuclk_get_rate()
428 		ret = rockchip_pll_set_rate(&rk3568_pll_clks[HPLL],  in rk3568_pmuclk_set_rate()
429 					    priv->pmucru, HPLL, rate);  in rk3568_pmuclk_set_rate()
430 		priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL],  in rk3568_pmuclk_set_rate()
431 						      priv->pmucru, HPLL);  in rk3568_pmuclk_set_rate()
1797 		parent = rk3568_pmu_pll_get_rate(priv, HPLL);  in rk3568_dclk_vop_get_clk()
1843 		rk3568_pmu_pll_set_rate(priv, HPLL, div * rate);  in rk3568_dclk_vop_set_clk()
1909 		return rk3568_pmu_pll_get_rate(priv, HPLL);  in rk3568_gmac_src_get_clk()
3268 	priv->hpll_hz = rk3568_pmu_pll_get_rate(priv, HPLL);  in rk3568_clk_init()