Lines Matching full:rate
25 .rate = _rate##U, \
118 ulong pll_id, ulong rate) in rk3568_pmu_pll_set_rate() argument
134 pmu_priv->pmucru, pll_id, rate); in rk3568_pmu_pll_set_rate()
226 ulong rate) in rk3568_rtc32k_set_pmuclk() argument
234 rational_best_approximation(rate, OSC_HZ, in rk3568_rtc32k_set_pmuclk()
263 ulong clk_id, ulong rate) in rk3568_i2c_set_pmuclk() argument
268 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
307 ulong clk_id, ulong rate) in rk3568_pwm_set_pmuclk() argument
314 if (rate == OSC_HZ) { in rk3568_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
353 ulong rate) in rk3568_pmu_set_pmuclk() argument
358 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pmu_set_pmuclk()
372 ulong rate = 0; in rk3568_pmuclk_get_rate() local
382 rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_get_rate()
386 rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_get_rate()
391 rate = rk3568_rtc32k_get_pmuclk(priv); in rk3568_pmuclk_get_rate()
394 rate = rk3568_i2c_get_pmuclk(priv, clk->id); in rk3568_pmuclk_get_rate()
397 rate = rk3568_pwm_get_pmuclk(priv, clk->id); in rk3568_pmuclk_get_rate()
400 rate = rk3568_pmu_get_pmuclk(priv); in rk3568_pmuclk_get_rate()
406 return rate; in rk3568_pmuclk_get_rate()
409 static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) in rk3568_pmuclk_set_rate() argument
419 debug("%s %ld %ld\n", __func__, clk->id, rate); in rk3568_pmuclk_set_rate()
423 priv->pmucru, PPLL, rate); in rk3568_pmuclk_set_rate()
429 priv->pmucru, HPLL, rate); in rk3568_pmuclk_set_rate()
435 ret = rk3568_rtc32k_set_pmuclk(priv, rate); in rk3568_pmuclk_set_rate()
438 ret = rk3568_i2c_set_pmuclk(priv, clk->id, rate); in rk3568_pmuclk_set_rate()
441 ret = rk3568_pwm_set_pmuclk(priv, clk->id, rate); in rk3568_pmuclk_set_rate()
444 ret = rk3568_pmu_set_pmuclk(priv, rate); in rk3568_pmuclk_set_rate()
552 const struct rockchip_cpu_rate_table *rate; in rk3568_armclk_set_clk() local
555 rate = rockchip_get_cpu_settings(rk3568_cpu_rates, hz); in rk3568_armclk_set_clk()
556 if (!rate) { in rk3568_armclk_set_clk()
557 printf("%s unsupported rate\n", __func__); in rk3568_armclk_set_clk()
585 rate->pclk_div << GICCLK_CORE_DIV_SHIFT | in rk3568_armclk_set_clk()
586 rate->pclk_div << ATCLK_CORE_DIV_SHIFT); in rk3568_armclk_set_clk()
590 rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | in rk3568_armclk_set_clk()
591 rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); in rk3568_armclk_set_clk()
594 rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); in rk3568_armclk_set_clk()
598 rate->pclk_div << GICCLK_CORE_DIV_SHIFT | in rk3568_armclk_set_clk()
599 rate->pclk_div << ATCLK_CORE_DIV_SHIFT); in rk3568_armclk_set_clk()
603 rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | in rk3568_armclk_set_clk()
604 rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); in rk3568_armclk_set_clk()
607 rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); in rk3568_armclk_set_clk()
672 ulong clk_id, ulong rate) in rk3568_cpll_div_set_rate() argument
722 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_cpll_div_set_rate()
732 u32 con, sel, rate; in rk3568_bus_get_clk() local
739 rate = 200 * MHz; in rk3568_bus_get_clk()
741 rate = 150 * MHz; in rk3568_bus_get_clk()
743 rate = 100 * MHz; in rk3568_bus_get_clk()
745 rate = OSC_HZ; in rk3568_bus_get_clk()
752 rate = 100 * MHz; in rk3568_bus_get_clk()
754 rate = 75 * MHz; in rk3568_bus_get_clk()
756 rate = 50 * MHz; in rk3568_bus_get_clk()
758 rate = OSC_HZ; in rk3568_bus_get_clk()
764 return rate; in rk3568_bus_get_clk()
768 ulong clk_id, ulong rate) in rk3568_bus_set_clk() argument
775 if (rate == 200 * MHz) in rk3568_bus_set_clk()
777 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
779 else if (rate == 100 * MHz) in rk3568_bus_set_clk()
789 if (rate == 100 * MHz) in rk3568_bus_set_clk()
791 else if (rate == 75 * MHz) in rk3568_bus_set_clk()
793 else if (rate == 50 * MHz) in rk3568_bus_set_clk()
813 u32 con, sel, rate; in rk3568_perimid_get_clk() local
820 rate = 300 * MHz; in rk3568_perimid_get_clk()
822 rate = 200 * MHz; in rk3568_perimid_get_clk()
824 rate = 100 * MHz; in rk3568_perimid_get_clk()
826 rate = OSC_HZ; in rk3568_perimid_get_clk()
832 rate = 150 * MHz; in rk3568_perimid_get_clk()
834 rate = 100 * MHz; in rk3568_perimid_get_clk()
836 rate = 75 * MHz; in rk3568_perimid_get_clk()
838 rate = OSC_HZ; in rk3568_perimid_get_clk()
844 return rate; in rk3568_perimid_get_clk()
848 ulong clk_id, ulong rate) in rk3568_perimid_set_clk() argument
855 if (rate == 300 * MHz) in rk3568_perimid_set_clk()
857 else if (rate == 200 * MHz) in rk3568_perimid_set_clk()
859 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
868 if (rate == 150 * MHz) in rk3568_perimid_set_clk()
870 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
872 else if (rate == 75 * MHz) in rk3568_perimid_set_clk()
892 u32 con, sel, rate; in rk3568_top_get_clk() local
899 rate = 500 * MHz; in rk3568_top_get_clk()
901 rate = 400 * MHz; in rk3568_top_get_clk()
903 rate = 300 * MHz; in rk3568_top_get_clk()
905 rate = OSC_HZ; in rk3568_top_get_clk()
911 rate = 400 * MHz; in rk3568_top_get_clk()
913 rate = 300 * MHz; in rk3568_top_get_clk()
915 rate = 200 * MHz; in rk3568_top_get_clk()
917 rate = OSC_HZ; in rk3568_top_get_clk()
923 rate = 150 * MHz; in rk3568_top_get_clk()
925 rate = 100 * MHz; in rk3568_top_get_clk()
927 rate = 75 * MHz; in rk3568_top_get_clk()
929 rate = OSC_HZ; in rk3568_top_get_clk()
935 rate = 100 * MHz; in rk3568_top_get_clk()
937 rate = 75 * MHz; in rk3568_top_get_clk()
939 rate = 50 * MHz; in rk3568_top_get_clk()
941 rate = OSC_HZ; in rk3568_top_get_clk()
947 return rate; in rk3568_top_get_clk()
951 ulong clk_id, ulong rate) in rk3568_top_set_clk() argument
958 if (rate == 500 * MHz) in rk3568_top_set_clk()
960 else if (rate == 400 * MHz) in rk3568_top_set_clk()
962 else if (rate == 300 * MHz) in rk3568_top_set_clk()
971 if (rate == 400 * MHz) in rk3568_top_set_clk()
973 else if (rate == 300 * MHz) in rk3568_top_set_clk()
975 else if (rate == 200 * MHz) in rk3568_top_set_clk()
984 if (rate == 150 * MHz) in rk3568_top_set_clk()
986 else if (rate == 100 * MHz) in rk3568_top_set_clk()
988 else if (rate == 75 * MHz) in rk3568_top_set_clk()
997 if (rate == 100 * MHz) in rk3568_top_set_clk()
999 else if (rate == 75 * MHz) in rk3568_top_set_clk()
1001 else if (rate == 50 * MHz) in rk3568_top_set_clk()
1022 ulong rate; in rk3568_i2c_get_clk() local
1033 rate = 200 * MHz; in rk3568_i2c_get_clk()
1035 rate = 100 * MHz; in rk3568_i2c_get_clk()
1037 rate = 100 * MHz; in rk3568_i2c_get_clk()
1039 rate = OSC_HZ; in rk3568_i2c_get_clk()
1045 return rate; in rk3568_i2c_get_clk()
1049 ulong rate) in rk3568_i2c_set_clk() argument
1054 if (rate == 200 * MHz) in rk3568_i2c_set_clk()
1056 else if (rate == 100 * MHz) in rk3568_i2c_set_clk()
1114 ulong clk_id, ulong rate) in rk3568_spi_set_clk() argument
1119 if (rate == 200 * MHz) in rk3568_spi_set_clk()
1121 else if (rate == 100 * MHz) in rk3568_spi_set_clk()
1188 ulong clk_id, ulong rate) in rk3568_pwm_set_clk() argument
1193 if (rate == 100 * MHz) in rk3568_pwm_set_clk()
1251 ulong clk_id, ulong rate) in rk3568_adc_set_clk() argument
1261 if (!(OSC_HZ % rate)) { in rk3568_adc_set_clk()
1262 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3568_adc_set_clk()
1272 src_clk_div = DIV_ROUND_UP(100 * MHz, rate); in rk3568_adc_set_clk()
1285 src_clk_div = DIV_ROUND_UP(prate, rate); in rk3568_adc_set_clk()
1356 ulong clk_id, ulong rate) in rk3568_crypto_set_rate() argument
1366 if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1368 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1370 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1380 if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1382 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1384 else if (rate == 75 * MHz) in rk3568_crypto_set_rate()
1392 if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1394 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1402 if (rate == 300 * MHz) in rk3568_crypto_set_rate()
1404 else if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1460 ulong clk_id, ulong rate) in rk3568_sdmmc_set_clk() argument
1465 switch (rate) { in rk3568_sdmmc_set_clk()
1540 static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_sfc_set_clk() argument
1545 switch (rate) { in rk3568_sfc_set_clk()
1596 static ulong rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_nand_set_clk() argument
1601 switch (rate) { in rk3568_nand_set_clk()
1650 static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_emmc_set_clk() argument
1655 switch (rate) { in rk3568_emmc_set_clk()
1706 static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_emmc_set_bclk() argument
1711 switch (rate) { in rk3568_emmc_set_bclk()
1753 static ulong rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_aclk_vop_set_clk() argument
1758 if ((priv->cpll_hz % rate) == 0) { in rk3568_aclk_vop_set_clk()
1759 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_aclk_vop_set_clk()
1762 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_aclk_vop_set_clk()
1814 ulong clk_id, ulong rate) in rk3568_dclk_vop_set_clk() argument
1843 rk3568_pmu_pll_set_rate(priv, HPLL, div * rate); in rk3568_dclk_vop_set_clk()
1845 div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate); in rk3568_dclk_vop_set_clk()
1851 priv->cru, VPLL, div * rate); in rk3568_dclk_vop_set_clk()
1866 div = DIV_ROUND_UP(pll_rate, rate); in rk3568_dclk_vop_set_clk()
1870 if (abs(rate - now) < abs(rate - best_rate)) { in rk3568_dclk_vop_set_clk()
1885 printf("do not support this vop freq %lu\n", rate); in rk3568_dclk_vop_set_clk()
1916 ulong mac_id, ulong rate) in rk3568_gmac_src_set_clk() argument
1921 switch (rate) { in rk3568_gmac_src_set_clk()
1966 ulong mac_id, ulong rate) in rk3568_gmac_out_set_clk() argument
1971 switch (rate) { in rk3568_gmac_out_set_clk()
2019 ulong mac_id, ulong rate) in rk3568_gmac_ptp_ref_set_clk() argument
2024 switch (rate) { in rk3568_gmac_ptp_ref_set_clk()
2049 ulong mac_id, ulong rate) in rk3568_gmac_tx_rx_set_clk() argument
2058 if (rate == 2500000) in rk3568_gmac_tx_rx_set_clk()
2060 else if (rate == 25000000) in rk3568_gmac_tx_rx_set_clk()
2068 if (rate == 2500000) in rk3568_gmac_tx_rx_set_clk()
2103 static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_ebc_set_clk() argument
2108 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_ebc_set_clk()
2157 ulong clk_id, ulong rate) in rk3568_rkvdec_set_clk() argument
2171 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2190 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2267 ulong clk_id, ulong rate) in rk3568_uart_set_rate() argument
2273 if (priv->gpll_hz % rate == 0) { in rk3568_uart_set_rate()
2276 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_uart_set_rate()
2277 } else if (priv->cpll_hz % rate == 0) { in rk3568_uart_set_rate()
2280 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_uart_set_rate()
2281 } else if (rate == OSC_HZ) { in rk3568_uart_set_rate()
2289 rational_best_approximation(rate, priv->gpll_hz / div, in rk3568_uart_set_rate()
2411 ulong clk_id, ulong rate) in rk3568_i2s3_set_rate() argument
2418 if (priv->gpll_hz % rate == 0) { in rk3568_i2s3_set_rate()
2421 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_i2s3_set_rate()
2422 } else if (priv->cpll_hz % rate == 0) { in rk3568_i2s3_set_rate()
2425 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_i2s3_set_rate()
2426 } else if (rate == OSC_HZ / 2) { in rk3568_i2s3_set_rate()
2434 rational_best_approximation(rate, priv->gpll_hz / div, in rk3568_i2s3_set_rate()
2442 if (rate == 12000000) { in rk3568_i2s3_set_rate()
2448 rk3568_i2s3_set_rate(priv, MCLK_I2S3_2CH_TX, rate), in rk3568_i2s3_set_rate()
2456 if (rate == 12000000) { in rk3568_i2s3_set_rate()
2462 rk3568_i2s3_set_rate(priv, MCLK_I2S3_2CH_RX, rate), in rk3568_i2s3_set_rate()
2474 rk3568_i2s3_set_rate(priv, I2S3_MCLKOUT_RX, rate); in rk3568_i2s3_set_rate()
2476 rk3568_i2s3_set_rate(priv, I2S3_MCLKOUT_TX, rate); in rk3568_i2s3_set_rate()
2506 ulong rate = 0; in rk3568_clk_get_rate() local
2516 rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru, in rk3568_clk_get_rate()
2520 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2524 rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_get_rate()
2528 rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_get_rate()
2532 rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_get_rate()
2536 rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru, in rk3568_clk_get_rate()
2542 rate = rk3568_bus_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2546 rate = rk3568_perimid_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2552 rate = rk3568_top_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2559 rate = rk3568_i2c_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2565 rate = rk3568_spi_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2570 rate = rk3568_pwm_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2575 rate = rk3568_adc_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2581 rate = rk3568_sdmmc_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2584 rate = rk3568_sfc_get_clk(priv); in rk3568_clk_get_rate()
2587 rate = rk3568_nand_get_clk(priv); in rk3568_clk_get_rate()
2590 rate = rk3568_emmc_get_clk(priv); in rk3568_clk_get_rate()
2593 rate = rk3568_emmc_get_bclk(priv); in rk3568_clk_get_rate()
2596 rate = OSC_HZ; in rk3568_clk_get_rate()
2600 rate = rk3568_aclk_vop_get_clk(priv); in rk3568_clk_get_rate()
2605 rate = rk3568_dclk_vop_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2610 rate = rk3568_gmac_src_get_clk(priv, 0); in rk3568_clk_get_rate()
2613 rate = rk3568_gmac_out_get_clk(priv, 0); in rk3568_clk_get_rate()
2616 rate = rk3568_gmac_ptp_ref_get_clk(priv, 0); in rk3568_clk_get_rate()
2621 rate = rk3568_gmac_src_get_clk(priv, 1); in rk3568_clk_get_rate()
2624 rate = rk3568_gmac_out_get_clk(priv, 1); in rk3568_clk_get_rate()
2627 rate = rk3568_gmac_ptp_ref_get_clk(priv, 1); in rk3568_clk_get_rate()
2630 rate = rk3568_ebc_get_clk(priv); in rk3568_clk_get_rate()
2635 rate = rk3568_rkvdec_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2638 rate = OSC_HZ; in rk3568_clk_get_rate()
2649 rate = rk3568_uart_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2656 rate = rk3568_i2s3_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2666 rate = rk3568_crypto_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2676 rate = rk3568_cpll_div_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2682 return rate; in rk3568_clk_get_rate()
2685 static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) in rk3568_clk_set_rate() argument
2699 rk3568_armclk_set_clk(priv, rate); in rk3568_clk_set_rate()
2700 priv->armclk_hz = rate; in rk3568_clk_set_rate()
2704 CPLL, rate); in rk3568_clk_set_rate()
2710 GPLL, rate); in rk3568_clk_set_rate()
2716 NPLL, rate); in rk3568_clk_set_rate()
2720 VPLL, rate); in rk3568_clk_set_rate()
2728 ret = rk3568_bus_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2732 ret = rk3568_perimid_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2738 ret = rk3568_top_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2745 ret = rk3568_i2c_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2751 ret = rk3568_spi_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2756 ret = rk3568_pwm_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2761 ret = rk3568_adc_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2767 ret = rk3568_sdmmc_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2770 ret = rk3568_sfc_set_clk(priv, rate); in rk3568_clk_set_rate()
2773 ret = rk3568_nand_set_clk(priv, rate); in rk3568_clk_set_rate()
2776 ret = rk3568_emmc_set_clk(priv, rate); in rk3568_clk_set_rate()
2779 ret = rk3568_emmc_set_bclk(priv, rate); in rk3568_clk_set_rate()
2786 ret = rk3568_aclk_vop_set_clk(priv, rate); in rk3568_clk_set_rate()
2791 ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2796 ret = rk3568_gmac_src_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2799 ret = rk3568_gmac_out_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2802 ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2805 ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2810 ret = rk3568_gmac_src_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2813 ret = rk3568_gmac_out_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2816 ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2819 ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2822 ret = rk3568_ebc_set_clk(priv, rate); in rk3568_clk_set_rate()
2827 ret = rk3568_rkvdec_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2841 ret = rk3568_uart_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2848 ret = rk3568_i2s3_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2858 ret = rk3568_crypto_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2868 ret = rk3568_cpll_div_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2895 ulong rate; in rk3568_mmc_get_phase() local
2897 rate = rk3568_clk_get_rate(clk); in rk3568_mmc_get_phase()
2898 if (rate < 0) in rk3568_mmc_get_phase()
2899 return rate; in rk3568_mmc_get_phase()
2916 36 * (rate / 1000000); in rk3568_mmc_get_phase()
2932 ulong rate; in rk3568_mmc_set_phase() local
2934 rate = rk3568_clk_get_rate(clk); in rk3568_mmc_set_phase()
2935 if (rate < 0) in rk3568_mmc_set_phase()
2936 return rate; in rk3568_mmc_set_phase()
2947 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3568_mmc_set_phase()
3367 unsigned long rate; in soc_clk_dump() local
3404 rate = clk_get_rate(&clk); in soc_clk_dump()
3407 if (rate < 0) in soc_clk_dump()
3412 rate / 1000); in soc_clk_dump()
3414 if (rate < 0) in soc_clk_dump()
3419 rate / 1000); in soc_clk_dump()