Lines Matching refs:hpll_hz
971 parent = priv->hpll_hz; in rk3562_emmc_get_rate()
1005 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1006 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_emmc_set_rate()
1067 prate = priv->hpll_hz; in rk3562_sdmmc_get_rate()
1086 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_sdmmc_set_rate()
1087 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_sdmmc_set_rate()
1132 prate = priv->hpll_hz; in rk3562_vop_get_rate()
1160 prate = priv->hpll_hz; in rk3562_vop_get_rate()
1183 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1184 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_vop_set_rate()
1215 pll_rate = priv->hpll_hz; in rk3562_vop_set_rate()
1354 if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) { in rk3562_clk_get_rate()
1356 __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz); in rk3562_clk_get_rate()
1478 if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) { in rk3562_clk_set_rate()
1480 __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz); in rk3562_clk_set_rate()
1508 priv->hpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], in rk3562_clk_set_rate()
1833 if (priv->hpll_hz != HPLL_HZ) { in rk3562_clk_init()
1837 priv->hpll_hz = HPLL_HZ; in rk3562_clk_init()