Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
8 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3562-cru.h>
20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
105 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
156 struct rk3562_cru *cru = priv->cru; in rk3562_armclk_set_rate()
162 return -EINVAL; in rk3562_armclk_set_rate()
168 old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_armclk_set_rate()
171 rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK, in rk3562_armclk_set_rate()
172 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
173 rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK, in rk3562_armclk_set_rate()
174 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
175 rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0); in rk3562_armclk_set_rate()
178 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
179 return -EINVAL; in rk3562_armclk_set_rate()
180 rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK, in rk3562_armclk_set_rate()
181 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
182 rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK, in rk3562_armclk_set_rate()
183 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
184 rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0); in rk3562_armclk_set_rate()
186 rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK, in rk3562_armclk_set_rate()
187 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
188 rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK, in rk3562_armclk_set_rate()
189 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
190 rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0); in rk3562_armclk_set_rate()
193 priv->cru, APLL, new_rate)) in rk3562_armclk_set_rate()
194 return -EINVAL; in rk3562_armclk_set_rate()
202 struct rk3562_cru *cru = priv->cru; in rk3562_bus_get_rate()
203 u32 sel, con, div; in rk3562_bus_get_rate() local
208 con = readl(&cru->clksel_con[40]); in rk3562_bus_get_rate()
210 div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
213 con = readl(&cru->clksel_con[40]); in rk3562_bus_get_rate()
215 div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
218 con = readl(&cru->clksel_con[41]); in rk3562_bus_get_rate()
220 div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
223 return -ENOENT; in rk3562_bus_get_rate()
227 rate = priv->cpll_hz; in rk3562_bus_get_rate()
229 rate = priv->gpll_hz; in rk3562_bus_get_rate()
231 return DIV_TO_RATE(rate, div); in rk3562_bus_get_rate()
237 struct rk3562_cru *cru = priv->cru; in rk3562_bus_set_rate()
238 u32 sel, div; in rk3562_bus_set_rate() local
240 if (priv->cpll_hz % rate == 0) { in rk3562_bus_set_rate()
242 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_bus_set_rate()
245 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_bus_set_rate()
250 rk_clrsetreg(&cru->clksel_con[40], in rk3562_bus_set_rate()
253 ((div - 1) << ACLK_BUS_DIV_SHIFT)); in rk3562_bus_set_rate()
256 rk_clrsetreg(&cru->clksel_con[40], in rk3562_bus_set_rate()
259 ((div - 1) << HCLK_BUS_DIV_SHIFT)); in rk3562_bus_set_rate()
262 rk_clrsetreg(&cru->clksel_con[41], in rk3562_bus_set_rate()
265 ((div - 1) << PCLK_BUS_DIV_SHIFT)); in rk3562_bus_set_rate()
268 return -ENOENT; in rk3562_bus_set_rate()
276 struct rk3562_cru *cru = priv->cru; in rk3562_peri_get_rate()
277 u32 sel, con, div; in rk3562_peri_get_rate() local
282 con = readl(&cru->periclksel_con[0]); in rk3562_peri_get_rate()
284 div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT; in rk3562_peri_get_rate()
287 con = readl(&cru->periclksel_con[0]); in rk3562_peri_get_rate()
289 div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT; in rk3562_peri_get_rate()
292 con = readl(&cru->periclksel_con[1]); in rk3562_peri_get_rate()
294 div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT; in rk3562_peri_get_rate()
297 return -ENOENT; in rk3562_peri_get_rate()
301 rate = priv->cpll_hz; in rk3562_peri_get_rate()
303 rate = priv->gpll_hz; in rk3562_peri_get_rate()
305 return DIV_TO_RATE(rate, div); in rk3562_peri_get_rate()
311 struct rk3562_cru *cru = priv->cru; in rk3562_peri_set_rate()
312 u32 sel, div; in rk3562_peri_set_rate() local
314 if (priv->cpll_hz % rate == 0) { in rk3562_peri_set_rate()
316 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_peri_set_rate()
319 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_peri_set_rate()
324 rk_clrsetreg(&cru->periclksel_con[0], in rk3562_peri_set_rate()
327 ((div - 1) << ACLK_PERI_DIV_SHIFT)); in rk3562_peri_set_rate()
330 rk_clrsetreg(&cru->periclksel_con[0], in rk3562_peri_set_rate()
333 ((div - 1) << HCLK_PERI_DIV_SHIFT)); in rk3562_peri_set_rate()
336 rk_clrsetreg(&cru->periclksel_con[1], in rk3562_peri_set_rate()
339 ((div - 1) << PCLK_PERI_DIV_SHIFT)); in rk3562_peri_set_rate()
342 return -ENOENT; in rk3562_peri_set_rate()
350 struct rk3562_cru *cru = priv->cru; in rk3562_i2c_get_rate()
351 u32 sel, con, div; in rk3562_i2c_get_rate() local
356 con = readl(&cru->pmu0clksel_con[3]); in rk3562_i2c_get_rate()
364 div = (con & CLK_PMU0_I2C0_DIV_MASK) >> CLK_PMU0_I2C0_DIV_SHIFT; in rk3562_i2c_get_rate()
366 return DIV_TO_RATE(rate, div); in rk3562_i2c_get_rate()
373 con = readl(&cru->clksel_con[41]); in rk3562_i2c_get_rate()
385 return -ENOENT; in rk3562_i2c_get_rate()
394 struct rk3562_cru *cru = priv->cru; in rk3562_i2c_set_rate()
395 u32 sel, div; in rk3562_i2c_set_rate() local
401 div = 1; in rk3562_i2c_set_rate()
404 div = 1; in rk3562_i2c_set_rate()
407 div = 1; in rk3562_i2c_set_rate()
410 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_i2c_set_rate()
411 assert(div - 1 <= 31); in rk3562_i2c_set_rate()
413 rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_DIV_MASK, in rk3562_i2c_set_rate()
414 (div - 1) << CLK_PMU0_I2C0_DIV_SHIFT); in rk3562_i2c_set_rate()
415 rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_SEL_MASK, in rk3562_i2c_set_rate()
431 rk_clrsetreg(&cru->clksel_con[41], CLK_I2C_SEL_MASK, in rk3562_i2c_set_rate()
435 return -ENOENT; in rk3562_i2c_set_rate()
444 struct rk3562_cru *cru = priv->cru; in rk3562_uart_get_rate()
445 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3562_uart_get_rate() local
450 con = readl(&cru->pmu1clksel_con[2]); in rk3562_uart_get_rate()
453 div = (con & CLK_PMU1_UART0_SRC_DIV_MASK) >> in rk3562_uart_get_rate()
456 return DIV_TO_RATE(priv->cpll_hz, div); in rk3562_uart_get_rate()
458 fracdiv = readl(&cru->pmu1clksel_con[3]); in rk3562_uart_get_rate()
463 return DIV_TO_RATE(priv->cpll_hz, div) * n / m; in rk3562_uart_get_rate()
495 return -ENOENT; in rk3562_uart_get_rate()
497 con = readl(&cru->periclksel_con[reg]); in rk3562_uart_get_rate()
499 div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT; in rk3562_uart_get_rate()
502 p_rate = priv->gpll_hz; in rk3562_uart_get_rate()
504 p_rate = priv->cpll_hz; in rk3562_uart_get_rate()
506 return DIV_TO_RATE(p_rate, div); in rk3562_uart_get_rate()
508 fracdiv = readl(&cru->periclksel_con[reg + 1]); in rk3562_uart_get_rate()
513 return DIV_TO_RATE(p_rate, div) * n / m; in rk3562_uart_get_rate()
522 struct rk3562_cru *cru = priv->cru; in rk3562_uart_set_rate()
523 u32 reg, clk_src, uart_src, div; in rk3562_uart_set_rate() local
528 if (priv->cpll_hz % rate == 0) { in rk3562_uart_set_rate()
530 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
533 div = 2; in rk3562_uart_set_rate()
536 div = 2; in rk3562_uart_set_rate()
537 rational_best_approximation(rate, priv->cpll_hz / div, in rk3562_uart_set_rate()
538 GENMASK(16 - 1, 0), in rk3562_uart_set_rate()
539 GENMASK(16 - 1, 0), in rk3562_uart_set_rate()
543 rk_clrsetreg(&cru->pmu1clksel_con[2], in rk3562_uart_set_rate()
547 ((div - 1) << CLK_PMU1_UART0_SRC_DIV_SHIFT)); in rk3562_uart_set_rate()
550 writel(val, &cru->pmu1clksel_con[3]); in rk3562_uart_set_rate()
582 return -ENOENT; in rk3562_uart_set_rate()
585 if (priv->gpll_hz % rate == 0) { in rk3562_uart_set_rate()
588 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_uart_set_rate()
589 } else if (priv->cpll_hz % rate == 0) { in rk3562_uart_set_rate()
592 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
596 div = 2; in rk3562_uart_set_rate()
600 div = 2; in rk3562_uart_set_rate()
601 rational_best_approximation(rate, priv->gpll_hz / div, in rk3562_uart_set_rate()
602 GENMASK(16 - 1, 0), in rk3562_uart_set_rate()
603 GENMASK(16 - 1, 0), in rk3562_uart_set_rate()
607 rk_clrsetreg(&cru->periclksel_con[reg], in rk3562_uart_set_rate()
612 ((div - 1) << CLK_UART_SRC_DIV_SHIFT)); in rk3562_uart_set_rate()
615 writel(val, &cru->periclksel_con[reg + 1]); in rk3562_uart_set_rate()
623 struct rk3562_cru *cru = priv->cru; in rk3562_pwm_get_rate()
624 u32 sel, con, div, mask, shift; in rk3562_pwm_get_rate() local
629 con = readl(&cru->pmu1clksel_con[4]); in rk3562_pwm_get_rate()
637 div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT; in rk3562_pwm_get_rate()
639 return DIV_TO_RATE(rate, div); in rk3562_pwm_get_rate()
653 return -ENOENT; in rk3562_pwm_get_rate()
656 con = readl(&cru->periclksel_con[40]); in rk3562_pwm_get_rate()
671 struct rk3562_cru *cru = priv->cru; in rk3562_pwm_set_rate()
672 u32 sel, div, mask, shift; in rk3562_pwm_set_rate() local
678 div = 1; in rk3562_pwm_set_rate()
681 div = 1; in rk3562_pwm_set_rate()
684 div = 1; in rk3562_pwm_set_rate()
687 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_pwm_set_rate()
688 assert(div - 1 <= 3); in rk3562_pwm_set_rate()
690 rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_DIV_MASK, in rk3562_pwm_set_rate()
691 (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT); in rk3562_pwm_set_rate()
692 rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_SEL_MASK, in rk3562_pwm_set_rate()
709 return -ENOENT; in rk3562_pwm_set_rate()
718 rk_clrsetreg(&cru->periclksel_con[40], mask, sel << shift); in rk3562_pwm_set_rate()
725 struct rk3562_cru *cru = priv->cru; in rk3562_spi_get_rate()
726 u32 sel, con, div, mask, shift; in rk3562_spi_get_rate() local
731 con = readl(&cru->pmu1clksel_con[4]); in rk3562_spi_get_rate()
739 div = (con & CLK_PMU1_SPI0_DIV_MASK) >> CLK_PMU1_SPI0_DIV_SHIFT; in rk3562_spi_get_rate()
741 return DIV_TO_RATE(rate, div); in rk3562_spi_get_rate()
751 return -ENOENT; in rk3562_spi_get_rate()
754 con = readl(&cru->periclksel_con[20]); in rk3562_spi_get_rate()
771 struct rk3562_cru *cru = priv->cru; in rk3562_spi_set_rate()
772 u32 sel, div, mask, shift; in rk3562_spi_set_rate() local
778 div = 1; in rk3562_spi_set_rate()
781 div = 1; in rk3562_spi_set_rate()
784 div = 1; in rk3562_spi_set_rate()
787 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_spi_set_rate()
788 assert(div - 1 <= 3); in rk3562_spi_set_rate()
790 rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_DIV_MASK, in rk3562_spi_set_rate()
791 (div - 1) << CLK_PMU1_SPI0_DIV_SHIFT); in rk3562_spi_set_rate()
792 rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_SEL_MASK, in rk3562_spi_set_rate()
805 return -ENOENT; in rk3562_spi_set_rate()
816 rk_clrsetreg(&cru->periclksel_con[20], mask, sel << shift); in rk3562_spi_set_rate()
823 struct rk3562_cru *cru = priv->cru; in rk3562_tsadc_get_rate()
824 u32 div, con; in rk3562_tsadc_get_rate() local
826 con = readl(&cru->clksel_con[43]); in rk3562_tsadc_get_rate()
829 div = (con & CLK_TSADC_TSEN_DIV_MASK) >> in rk3562_tsadc_get_rate()
833 div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT; in rk3562_tsadc_get_rate()
836 return -ENOENT; in rk3562_tsadc_get_rate()
839 return DIV_TO_RATE(OSC_HZ, div); in rk3562_tsadc_get_rate()
845 struct rk3562_cru *cru = priv->cru; in rk3562_tsadc_set_rate()
846 u32 div, mask, shift; in rk3562_tsadc_set_rate() local
858 return -ENOENT; in rk3562_tsadc_set_rate()
861 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_tsadc_set_rate()
862 rk_clrsetreg(&cru->clksel_con[43], mask, (div - 1) << shift); in rk3562_tsadc_set_rate()
869 struct rk3562_cru *cru = priv->cru; in rk3562_saradc_get_rate()
870 u32 div, con; in rk3562_saradc_get_rate() local
874 con = readl(&cru->clksel_con[44]); in rk3562_saradc_get_rate()
875 div = (con & CLK_SARADC_VCCIO156_DIV_MASK) >> in rk3562_saradc_get_rate()
879 con = readl(&cru->periclksel_con[46]); in rk3562_saradc_get_rate()
880 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3562_saradc_get_rate()
883 return -ENOENT; in rk3562_saradc_get_rate()
886 return DIV_TO_RATE(OSC_HZ, div); in rk3562_saradc_get_rate()
892 struct rk3562_cru *cru = priv->cru; in rk3562_saradc_set_rate()
893 u32 div; in rk3562_saradc_set_rate() local
897 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_saradc_set_rate()
898 rk_clrsetreg(&cru->clksel_con[44], CLK_SARADC_VCCIO156_DIV_MASK, in rk3562_saradc_set_rate()
899 (div - 1) << CLK_SARADC_VCCIO156_DIV_SHIFT); in rk3562_saradc_set_rate()
902 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_saradc_set_rate()
903 rk_clrsetreg(&cru->periclksel_con[46], CLK_SARADC_DIV_MASK, in rk3562_saradc_set_rate()
904 (div - 1) << CLK_SARADC_DIV_SHIFT); in rk3562_saradc_set_rate()
907 return -ENOENT; in rk3562_saradc_set_rate()
915 struct rk3562_cru *cru = priv->cru; in rk3562_sfc_get_rate()
916 u32 div, sel, con, parent; in rk3562_sfc_get_rate() local
918 con = readl(&cru->periclksel_con[20]); in rk3562_sfc_get_rate()
919 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rk3562_sfc_get_rate()
922 parent = priv->gpll_hz; in rk3562_sfc_get_rate()
924 parent = priv->cpll_hz; in rk3562_sfc_get_rate()
928 return DIV_TO_RATE(parent, div); in rk3562_sfc_get_rate()
933 struct rk3562_cru *cru = priv->cru; in rk3562_sfc_set_rate()
934 int div, sel; in rk3562_sfc_set_rate() local
937 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_sfc_set_rate()
939 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_sfc_set_rate()
940 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_sfc_set_rate()
943 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_sfc_set_rate()
947 assert(div - 1 <= 255); in rk3562_sfc_set_rate()
948 rk_clrsetreg(&cru->periclksel_con[20], in rk3562_sfc_set_rate()
951 (div - 1) << SCLK_SFC_DIV_SHIFT); in rk3562_sfc_set_rate()
958 struct rk3562_cru *cru = priv->cru; in rk3562_emmc_get_rate()
959 u32 div, sel, con, parent; in rk3562_emmc_get_rate() local
963 con = readl(&cru->periclksel_con[18]); in rk3562_emmc_get_rate()
964 div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; in rk3562_emmc_get_rate()
967 parent = priv->gpll_hz; in rk3562_emmc_get_rate()
969 parent = priv->cpll_hz; in rk3562_emmc_get_rate()
971 parent = priv->hpll_hz; in rk3562_emmc_get_rate()
976 con = readl(&cru->periclksel_con[19]); in rk3562_emmc_get_rate()
977 div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT; in rk3562_emmc_get_rate()
980 parent = priv->gpll_hz; in rk3562_emmc_get_rate()
982 parent = priv->cpll_hz; in rk3562_emmc_get_rate()
985 return -ENOENT; in rk3562_emmc_get_rate()
988 return DIV_TO_RATE(parent, div); in rk3562_emmc_get_rate()
994 struct rk3562_cru *cru = priv->cru; in rk3562_emmc_set_rate()
995 int div, sel; in rk3562_emmc_set_rate() local
1000 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_emmc_set_rate()
1002 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1003 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_emmc_set_rate()
1005 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1006 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_emmc_set_rate()
1009 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_emmc_set_rate()
1012 rk_clrsetreg(&cru->periclksel_con[18], in rk3562_emmc_set_rate()
1015 (div - 1) << CCLK_EMMC_DIV_SHIFT); in rk3562_emmc_set_rate()
1018 if ((priv->cpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1019 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_emmc_set_rate()
1022 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_emmc_set_rate()
1025 rk_clrsetreg(&cru->periclksel_con[19], in rk3562_emmc_set_rate()
1028 (div - 1) << BCLK_EMMC_DIV_SHIFT); in rk3562_emmc_set_rate()
1031 return -ENOENT; in rk3562_emmc_set_rate()
1039 struct rk3562_cru *cru = priv->cru; in rk3562_sdmmc_get_rate()
1040 u32 div, sel, con; in rk3562_sdmmc_get_rate() local
1047 con = readl(&cru->periclksel_con[16]); in rk3562_sdmmc_get_rate()
1048 div = (con & CCLK_SDMMC0_DIV_MASK) >> CCLK_SDMMC0_DIV_SHIFT; in rk3562_sdmmc_get_rate()
1054 con = readl(&cru->periclksel_con[17]); in rk3562_sdmmc_get_rate()
1055 div = (con & CCLK_SDMMC1_DIV_MASK) >> CCLK_SDMMC1_DIV_SHIFT; in rk3562_sdmmc_get_rate()
1059 return -ENOENT; in rk3562_sdmmc_get_rate()
1063 prate = priv->gpll_hz; in rk3562_sdmmc_get_rate()
1065 prate = priv->cpll_hz; in rk3562_sdmmc_get_rate()
1067 prate = priv->hpll_hz; in rk3562_sdmmc_get_rate()
1071 return DIV_TO_RATE(prate, div); in rk3562_sdmmc_get_rate()
1077 struct rk3562_cru *cru = priv->cru; in rk3562_sdmmc_set_rate()
1078 u32 div, sel; in rk3562_sdmmc_set_rate() local
1081 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_sdmmc_set_rate()
1083 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_sdmmc_set_rate()
1084 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_sdmmc_set_rate()
1086 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_sdmmc_set_rate()
1087 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_sdmmc_set_rate()
1090 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_sdmmc_set_rate()
1097 rk_clrsetreg(&cru->periclksel_con[16], in rk3562_sdmmc_set_rate()
1100 (div - 1) << CCLK_SDMMC0_DIV_SHIFT); in rk3562_sdmmc_set_rate()
1104 rk_clrsetreg(&cru->periclksel_con[17], in rk3562_sdmmc_set_rate()
1107 (div - 1) << CCLK_SDMMC1_DIV_SHIFT); in rk3562_sdmmc_set_rate()
1110 return -ENOENT; in rk3562_sdmmc_set_rate()
1118 struct rk3562_cru *cru = priv->cru; in rk3562_vop_get_rate()
1119 u32 con, sel, div; in rk3562_vop_get_rate() local
1124 con = readl(&cru->clksel_con[28]); in rk3562_vop_get_rate()
1125 div = (con & ACLK_VOP_DIV_MASK) >> ACLK_VOP_DIV_SHIFT; in rk3562_vop_get_rate()
1128 prate = priv->gpll_hz; in rk3562_vop_get_rate()
1130 prate = priv->cpll_hz; in rk3562_vop_get_rate()
1132 prate = priv->hpll_hz; in rk3562_vop_get_rate()
1134 prate = priv->vpll_hz; in rk3562_vop_get_rate()
1136 return -ENOENT; in rk3562_vop_get_rate()
1138 return DIV_TO_RATE(prate, div); in rk3562_vop_get_rate()
1140 con = readl(&cru->clksel_con[30]); in rk3562_vop_get_rate()
1141 div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; in rk3562_vop_get_rate()
1144 priv->vpll_hz = in rk3562_vop_get_rate()
1146 priv->cru, VPLL); in rk3562_vop_get_rate()
1149 con = readl(&cru->clksel_con[31]); in rk3562_vop_get_rate()
1150 div = (con & DCLK_VOP1_DIV_MASK) >> DCLK_VOP1_DIV_SHIFT; in rk3562_vop_get_rate()
1154 return -ENOENT; in rk3562_vop_get_rate()
1158 prate = priv->gpll_hz; in rk3562_vop_get_rate()
1160 prate = priv->hpll_hz; in rk3562_vop_get_rate()
1162 prate = priv->vpll_hz; in rk3562_vop_get_rate()
1164 return -ENOENT; in rk3562_vop_get_rate()
1166 return DIV_TO_RATE(prate, div); in rk3562_vop_get_rate()
1174 struct rk3562_cru *cru = priv->cru; in rk3562_vop_set_rate()
1175 u32 i, div, sel, best_div = 0, best_sel = 0; in rk3562_vop_set_rate() local
1180 if ((priv->cpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1181 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_vop_set_rate()
1183 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1184 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_vop_set_rate()
1186 } else if ((priv->vpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1187 div = DIV_ROUND_UP(priv->vpll_hz, rate); in rk3562_vop_set_rate()
1190 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_vop_set_rate()
1193 rk_clrsetreg(&cru->clksel_con[28], in rk3562_vop_set_rate()
1196 ((div - 1) << ACLK_VOP_DIV_SHIFT)); in rk3562_vop_set_rate()
1200 div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate); in rk3562_vop_set_rate()
1201 rk_clrsetreg(&cru->clksel_con[30], in rk3562_vop_set_rate()
1204 ((div - 1) << DCLK_VOP_DIV_SHIFT)); in rk3562_vop_set_rate()
1205 rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_vop_set_rate()
1206 VPLL, div * rate); in rk3562_vop_set_rate()
1212 pll_rate = priv->gpll_hz; in rk3562_vop_set_rate()
1215 pll_rate = priv->hpll_hz; in rk3562_vop_set_rate()
1222 return -EINVAL; in rk3562_vop_set_rate()
1225 div = DIV_ROUND_UP(pll_rate, rate); in rk3562_vop_set_rate()
1226 if (div > 255) in rk3562_vop_set_rate()
1228 now = pll_rate / div; in rk3562_vop_set_rate()
1229 if (abs(rate - now) < abs(rate - best_rate)) { in rk3562_vop_set_rate()
1231 best_div = div; in rk3562_vop_set_rate()
1234 debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n", in rk3562_vop_set_rate()
1238 rk_clrsetreg(&cru->clksel_con[31], in rk3562_vop_set_rate()
1241 (best_div - 1) << DCLK_VOP1_DIV_SHIFT); in rk3562_vop_set_rate()
1244 return -EINVAL; in rk3562_vop_set_rate()
1248 return -ENOENT; in rk3562_vop_set_rate()
1256 struct rk3562_cru *cru = priv->cru; in rk3562_gmac_get_rate()
1257 u32 con, sel, div; in rk3562_gmac_get_rate() local
1262 con = readl(&cru->clksel_con[45]); in rk3562_gmac_get_rate()
1269 con = readl(&cru->clksel_con[45]); in rk3562_gmac_get_rate()
1276 con = readl(&cru->clksel_con[47]); in rk3562_gmac_get_rate()
1283 con = readl(&cru->clksel_con[46]); in rk3562_gmac_get_rate()
1285 div = (con & CLK_GMAC_ETH_OUT2IO_DIV_MASK) >> CLK_GMAC_ETH_OUT2IO_DIV_SHIFT; in rk3562_gmac_get_rate()
1287 prate = priv->gpll_hz; in rk3562_gmac_get_rate()
1289 prate = priv->cpll_hz; in rk3562_gmac_get_rate()
1292 return -ENOENT; in rk3562_gmac_get_rate()
1295 return DIV_TO_RATE(prate, div); in rk3562_gmac_get_rate()
1301 struct rk3562_cru *cru = priv->cru; in rk3562_gmac_set_rate()
1302 u32 sel, div; in rk3562_gmac_set_rate() local
1310 rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_125M_SEL_MASK, in rk3562_gmac_set_rate()
1318 rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_50M_SEL_MASK, in rk3562_gmac_set_rate()
1326 rk_clrsetreg(&cru->clksel_con[47], CLK_GMAC_50M_SEL_MASK, in rk3562_gmac_set_rate()
1330 if ((priv->cpll_hz % rate) == 0) { in rk3562_gmac_set_rate()
1331 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_gmac_set_rate()
1334 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_gmac_set_rate()
1337 rk_clrsetreg(&cru->clksel_con[46], in rk3562_gmac_set_rate()
1340 (div - 1) << CLK_GMAC_ETH_OUT2IO_DIV_SHIFT); in rk3562_gmac_set_rate()
1343 return -ENOENT; in rk3562_gmac_set_rate()
1349 static ulong rk3562_clk_get_rate(struct clk *clk) in rk3562_clk_get_rate() argument
1351 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_clk_get_rate()
1354 if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) { in rk3562_clk_get_rate()
1356 __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz); in rk3562_clk_get_rate()
1357 return -ENOENT; in rk3562_clk_get_rate()
1360 switch (clk->id) { in rk3562_clk_get_rate()
1363 rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_clk_get_rate()
1367 rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_get_rate()
1372 rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_get_rate()
1376 rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_get_rate()
1380 rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_get_rate()
1384 rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru, in rk3562_clk_get_rate()
1390 rate = rk3562_bus_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1395 rate = rk3562_peri_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1404 rate = rk3562_i2c_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1416 rate = rk3562_uart_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1422 rate = rk3562_pwm_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1427 rate = rk3562_spi_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1431 rate = rk3562_tsadc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1435 rate = rk3562_saradc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1442 rate = rk3562_emmc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1450 rate = rk3562_sdmmc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1455 rate = rk3562_vop_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1461 rate = rk3562_gmac_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1467 return -ENOENT; in rk3562_clk_get_rate()
1473 static ulong rk3562_clk_set_rate(struct clk *clk, ulong rate) in rk3562_clk_set_rate() argument
1475 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_clk_set_rate()
1478 if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) { in rk3562_clk_set_rate()
1480 __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz); in rk3562_clk_set_rate()
1481 return -ENOENT; in rk3562_clk_set_rate()
1484 debug("%s: id=%ld, rate=%ld\n", __func__, clk->id, rate); in rk3562_clk_set_rate()
1486 switch (clk->id) { in rk3562_clk_set_rate()
1489 if (priv->armclk_hz) in rk3562_clk_set_rate()
1491 priv->armclk_hz = rate; in rk3562_clk_set_rate()
1494 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_set_rate()
1496 priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], in rk3562_clk_set_rate()
1497 priv->cru, GPLL); in rk3562_clk_set_rate()
1500 ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_set_rate()
1502 priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], in rk3562_clk_set_rate()
1503 priv->cru, VPLL); in rk3562_clk_set_rate()
1506 ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_set_rate()
1508 priv->hpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], in rk3562_clk_set_rate()
1509 priv->cru, HPLL); in rk3562_clk_set_rate()
1514 ret = rk3562_bus_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1519 ret = rk3562_peri_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1528 ret = rk3562_i2c_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1540 ret = rk3562_uart_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1546 ret = rk3562_pwm_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1551 ret = rk3562_spi_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1555 ret = rk3562_tsadc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1559 ret = rk3562_saradc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1566 ret = rk3562_emmc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1572 ret = rk3562_sdmmc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1577 ret = rk3562_vop_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1583 ret = rk3562_gmac_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1586 return -ENOENT; in rk3562_clk_set_rate()
1600 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1605 int rk3562_mmc_get_phase(struct clk *clk) in rk3562_mmc_get_phase() argument
1607 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_mmc_get_phase()
1608 struct rk3562_cru *cru = priv->cru; in rk3562_mmc_get_phase()
1613 rate = rk3562_clk_get_rate(clk); in rk3562_mmc_get_phase()
1617 if (clk->id == SCLK_SDMMC0_SAMPLE) in rk3562_mmc_get_phase()
1618 raw_value = readl(&cru->sdmmc0_con[1]); in rk3562_mmc_get_phase()
1619 else if (clk->id == SCLK_SDMMC0_SAMPLE) in rk3562_mmc_get_phase()
1620 raw_value = readl(&cru->sdmmc1_con[1]); in rk3562_mmc_get_phase()
1622 return -ENONET; in rk3562_mmc_get_phase()
1640 int rk3562_mmc_set_phase(struct clk *clk, u32 degrees) in rk3562_mmc_set_phase() argument
1642 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_mmc_set_phase()
1643 struct rk3562_cru *cru = priv->cru; in rk3562_mmc_set_phase()
1648 rate = rk3562_clk_get_rate(clk); in rk3562_mmc_set_phase()
1657 * don't overflow 32-bit / 64-bit numbers. in rk3562_mmc_set_phase()
1670 if (clk->id == SCLK_SDMMC0_SAMPLE) in rk3562_mmc_set_phase()
1671 writel(raw_value | 0xffff0000, &cru->sdmmc0_con[1]); in rk3562_mmc_set_phase()
1673 writel(raw_value | 0xffff0000, &cru->sdmmc1_con[1]); in rk3562_mmc_set_phase()
1676 degrees, delay_num, raw_value, rk3562_mmc_get_phase(clk)); in rk3562_mmc_set_phase()
1681 static int rk3562_clk_get_phase(struct clk *clk) in rk3562_clk_get_phase() argument
1685 switch (clk->id) { in rk3562_clk_get_phase()
1688 ret = rk3562_mmc_get_phase(clk); in rk3562_clk_get_phase()
1691 return -ENOENT; in rk3562_clk_get_phase()
1697 static int rk3562_clk_set_phase(struct clk *clk, int degrees) in rk3562_clk_set_phase() argument
1701 switch (clk->id) { in rk3562_clk_set_phase()
1704 ret = rk3562_mmc_set_phase(clk, degrees); in rk3562_clk_set_phase()
1707 return -ENOENT; in rk3562_clk_set_phase()
1722 * soc_clk_dump() - Print clock frequencies
1725 * Implementation for the clk dump command.
1732 struct clk clk; in soc_clk_dump() local
1746 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1747 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1748 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1749 priv->armclk_init_hz / 1000, in soc_clk_dump()
1750 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1751 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1754 if (clk_dump->name) { in soc_clk_dump()
1755 clk.id = clk_dump->id; in soc_clk_dump()
1756 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1760 rate = clk_get_rate(&clk); in soc_clk_dump()
1761 clk_free(&clk); in soc_clk_dump()
1764 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1767 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1771 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1774 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1788 priv->sync_kernel = false; in rk3562_clk_init()
1789 if (!priv->armclk_enter_hz) in rk3562_clk_init()
1790 priv->armclk_enter_hz = in rk3562_clk_init()
1792 priv->cru, APLL); in rk3562_clk_init()
1794 if (!priv->armclk_init_hz) { in rk3562_clk_init()
1798 priv->armclk_init_hz = APLL_HZ; in rk3562_clk_init()
1801 struct clk clk; in rk3562_clk_init()
1803 ret = rockchip_get_scmi_clk(&clk.dev); in rk3562_clk_init()
1805 printf("Failed to get scmi clk dev\n"); in rk3562_clk_init()
1809 clk.id = ARMCLK; in rk3562_clk_init()
1810 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); in rk3562_clk_init()
1815 priv->armclk_init_hz = CPU_PVTPLL_HZ; in rk3562_clk_init()
1819 if (priv->cpll_hz != CPLL_HZ) { in rk3562_clk_init()
1820 ret = rockchip_pll_set_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_init()
1823 priv->cpll_hz = CPLL_HZ; in rk3562_clk_init()
1826 if (priv->gpll_hz != GPLL_HZ) { in rk3562_clk_init()
1827 ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_init()
1830 priv->gpll_hz = GPLL_HZ; in rk3562_clk_init()
1833 if (priv->hpll_hz != HPLL_HZ) { in rk3562_clk_init()
1834 ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_init()
1837 priv->hpll_hz = HPLL_HZ; in rk3562_clk_init()
1848 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk3562_clk_probe()
1853 priv->sync_kernel = true; in rk3562_clk_probe()
1862 priv->cru = dev_read_addr_ptr(dev); in rk3562_clk_ofdata_to_platdata()
1881 priv->glb_srst_fst_value = offsetof(struct rk3562_cru, in rk3562_clk_bind()
1883 priv->glb_srst_snd_value = offsetof(struct rk3562_cru, in rk3562_clk_bind()
1885 sys_child->priv = priv; in rk3562_clk_bind()
1894 sf_priv->sf_reset_offset = offsetof(struct rk3562_cru, in rk3562_clk_bind()
1896 /* (0x30444 - 0x400) / 4 + 1 = 49170 */ in rk3562_clk_bind()
1897 sf_priv->sf_reset_num = 49170; in rk3562_clk_bind()
1898 sf_child->priv = sf_priv; in rk3562_clk_bind()
1905 { .compatible = "rockchip,rk3562-cru" },
1920 /* spl scmi clk */
1925 struct rk3562_cru *cru = priv->cru; in rk3562_crypto_get_rate()
1929 con = readl(&cru->periclksel_con[43]); in rk3562_crypto_get_rate()
1954 return -ENOENT; in rk3562_crypto_get_rate()
1963 struct rk3562_cru *cru = priv->cru; in rk3562_crypto_set_rate()
1990 return -ENOENT; in rk3562_crypto_set_rate()
1992 rk_clrsetreg(&cru->periclksel_con[43], mask, sel << shift); in rk3562_crypto_set_rate()
1997 static ulong rk3562_clk_scmi_get_rate(struct clk *clk) in rk3562_clk_scmi_get_rate() argument
1999 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_clk_scmi_get_rate()
2001 switch (clk->id) { in rk3562_clk_scmi_get_rate()
2004 return rk3562_crypto_get_rate(priv, clk->id); in rk3562_clk_scmi_get_rate()
2006 return -ENOENT; in rk3562_clk_scmi_get_rate()
2010 static ulong rk3562_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3562_clk_scmi_set_rate() argument
2012 struct rk3562_clk_priv *priv = dev_get_priv(clk->dev); in rk3562_clk_scmi_set_rate()
2014 switch (clk->id) { in rk3562_clk_scmi_set_rate()
2017 return rk3562_crypto_set_rate(priv, clk->id, rate); in rk3562_clk_scmi_set_rate()
2019 return -ENOENT; in rk3562_clk_scmi_set_rate()
2028 priv->cru = (struct rk3562_cru *)0xff100000; in rk3562_scmi_clk_ofdata_to_platdata()