20 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
203 	u32 sel, con, div;  in rk3562_bus_get_rate()  local
210 		div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
215 		div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
220 		div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT;  in rk3562_bus_get_rate()
231 	return DIV_TO_RATE(rate, div);  in rk3562_bus_get_rate()
238 	u32 sel, div;  in rk3562_bus_set_rate()  local
242 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_bus_set_rate()
245 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_bus_set_rate()
253 			     ((div - 1) << ACLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
259 			     ((div - 1) << HCLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
265 			     ((div - 1) << PCLK_BUS_DIV_SHIFT));  in rk3562_bus_set_rate()
277 	u32 sel, con, div;  in rk3562_peri_get_rate()  local
284 		div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
289 		div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
294 		div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;  in rk3562_peri_get_rate()
305 	return DIV_TO_RATE(rate, div);  in rk3562_peri_get_rate()
312 	u32 sel, div;  in rk3562_peri_set_rate()  local
316 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_peri_set_rate()
319 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_peri_set_rate()
327 			     ((div - 1) << ACLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
333 			     ((div - 1) << HCLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
339 			     ((div - 1) << PCLK_PERI_DIV_SHIFT));  in rk3562_peri_set_rate()
351 	u32 sel, con, div;  in rk3562_i2c_get_rate()  local
364 		div = (con & CLK_PMU0_I2C0_DIV_MASK) >> CLK_PMU0_I2C0_DIV_SHIFT;  in rk3562_i2c_get_rate()
366 		return DIV_TO_RATE(rate, div);  in rk3562_i2c_get_rate()
395 	u32 sel, div;  in rk3562_i2c_set_rate()  local
401 			div = 1;  in rk3562_i2c_set_rate()
404 			div = 1;  in rk3562_i2c_set_rate()
407 			div = 1;  in rk3562_i2c_set_rate()
410 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_i2c_set_rate()
411 			assert(div - 1 <= 31);  in rk3562_i2c_set_rate()
414 			     (div - 1) << CLK_PMU0_I2C0_DIV_SHIFT);  in rk3562_i2c_set_rate()
445 	u32 reg, con, fracdiv, div, src, p_src, p_rate;  in rk3562_uart_get_rate()  local
453 		div = (con & CLK_PMU1_UART0_SRC_DIV_MASK) >>  in rk3562_uart_get_rate()
456 			return DIV_TO_RATE(priv->cpll_hz, div);  in rk3562_uart_get_rate()
463 			return DIV_TO_RATE(priv->cpll_hz, div) * n / m;  in rk3562_uart_get_rate()
499 	div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;  in rk3562_uart_get_rate()
506 		return DIV_TO_RATE(p_rate, div);  in rk3562_uart_get_rate()
513 		return DIV_TO_RATE(p_rate, div) * n / m;  in rk3562_uart_get_rate()
523 	u32 reg, clk_src, uart_src, div;  in rk3562_uart_set_rate()  local
530 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_uart_set_rate()
533 			div = 2;  in rk3562_uart_set_rate()
536 			div = 2;  in rk3562_uart_set_rate()
537 			rational_best_approximation(rate, priv->cpll_hz / div,  in rk3562_uart_set_rate()
547 			     ((div - 1) << CLK_PMU1_UART0_SRC_DIV_SHIFT));  in rk3562_uart_set_rate()
588 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_uart_set_rate()
592 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_uart_set_rate()
596 		div = 2;  in rk3562_uart_set_rate()
600 		div = 2;  in rk3562_uart_set_rate()
601 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3562_uart_set_rate()
612 		     ((div - 1) << CLK_UART_SRC_DIV_SHIFT));  in rk3562_uart_set_rate()
624 	u32 sel, con, div, mask, shift;  in rk3562_pwm_get_rate()  local
637 		div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT;  in rk3562_pwm_get_rate()
639 		return DIV_TO_RATE(rate, div);  in rk3562_pwm_get_rate()
672 	u32 sel, div, mask, shift;  in rk3562_pwm_set_rate()  local
678 			div = 1;  in rk3562_pwm_set_rate()
681 			div = 1;  in rk3562_pwm_set_rate()
684 			div = 1;  in rk3562_pwm_set_rate()
687 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_pwm_set_rate()
688 			assert(div - 1 <= 3);  in rk3562_pwm_set_rate()
691 			     (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT);  in rk3562_pwm_set_rate()
726 	u32 sel, con, div, mask, shift;  in rk3562_spi_get_rate()  local
739 		div = (con & CLK_PMU1_SPI0_DIV_MASK) >> CLK_PMU1_SPI0_DIV_SHIFT;  in rk3562_spi_get_rate()
741 		return DIV_TO_RATE(rate, div);  in rk3562_spi_get_rate()
772 	u32 sel, div, mask, shift;  in rk3562_spi_set_rate()  local
778 			div = 1;  in rk3562_spi_set_rate()
781 			div = 1;  in rk3562_spi_set_rate()
784 			div = 1;  in rk3562_spi_set_rate()
787 			div = DIV_ROUND_UP(200 * MHz, rate);  in rk3562_spi_set_rate()
788 			assert(div - 1 <= 3);  in rk3562_spi_set_rate()
791 			     (div - 1) << CLK_PMU1_SPI0_DIV_SHIFT);  in rk3562_spi_set_rate()
824 	u32 div, con;  in rk3562_tsadc_get_rate()  local
829 		div = (con & CLK_TSADC_TSEN_DIV_MASK) >>  in rk3562_tsadc_get_rate()
833 		div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;  in rk3562_tsadc_get_rate()
839 	return DIV_TO_RATE(OSC_HZ, div);  in rk3562_tsadc_get_rate()
846 	u32 div, mask, shift;  in rk3562_tsadc_set_rate()  local
861 	div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_tsadc_set_rate()
862 	rk_clrsetreg(&cru->clksel_con[43], mask, (div - 1) << shift);  in rk3562_tsadc_set_rate()
870 	u32 div, con;  in rk3562_saradc_get_rate()  local
875 		div = (con & CLK_SARADC_VCCIO156_DIV_MASK) >>  in rk3562_saradc_get_rate()
880 		div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;  in rk3562_saradc_get_rate()
886 	return DIV_TO_RATE(OSC_HZ, div);  in rk3562_saradc_get_rate()
893 	u32 div;  in rk3562_saradc_set_rate()  local
897 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_saradc_set_rate()
899 			     (div - 1) << CLK_SARADC_VCCIO156_DIV_SHIFT);  in rk3562_saradc_set_rate()
902 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_saradc_set_rate()
904 			     (div - 1) << CLK_SARADC_DIV_SHIFT);  in rk3562_saradc_set_rate()
916 	u32 div, sel, con, parent;  in rk3562_sfc_get_rate()  local
919 	div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;  in rk3562_sfc_get_rate()
928 	return DIV_TO_RATE(parent, div);  in rk3562_sfc_get_rate()
934 	int div, sel;  in rk3562_sfc_set_rate()  local
937 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_sfc_set_rate()
940 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_sfc_set_rate()
943 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_sfc_set_rate()
947 	assert(div - 1 <= 255);  in rk3562_sfc_set_rate()
951 		     (div - 1) << SCLK_SFC_DIV_SHIFT);  in rk3562_sfc_set_rate()
959 	u32 div, sel, con, parent;  in rk3562_emmc_get_rate()  local
964 		div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;  in rk3562_emmc_get_rate()
977 		div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;  in rk3562_emmc_get_rate()
988 	return DIV_TO_RATE(parent, div);  in rk3562_emmc_get_rate()
995 	int div, sel;  in rk3562_emmc_set_rate()  local
1000 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_emmc_set_rate()
1003 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_emmc_set_rate()
1006 			div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_emmc_set_rate()
1009 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_emmc_set_rate()
1015 			     (div - 1) << CCLK_EMMC_DIV_SHIFT);  in rk3562_emmc_set_rate()
1019 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_emmc_set_rate()
1022 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_emmc_set_rate()
1028 			     (div - 1) << BCLK_EMMC_DIV_SHIFT);  in rk3562_emmc_set_rate()
1040 	u32 div, sel, con;  in rk3562_sdmmc_get_rate()  local
1048 		div = (con & CCLK_SDMMC0_DIV_MASK) >> CCLK_SDMMC0_DIV_SHIFT;  in rk3562_sdmmc_get_rate()
1055 		div = (con & CCLK_SDMMC1_DIV_MASK) >> CCLK_SDMMC1_DIV_SHIFT;  in rk3562_sdmmc_get_rate()
1071 	return DIV_TO_RATE(prate, div);  in rk3562_sdmmc_get_rate()
1078 	u32 div, sel;  in rk3562_sdmmc_set_rate()  local
1081 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3562_sdmmc_set_rate()
1084 		div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_sdmmc_set_rate()
1087 		div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_sdmmc_set_rate()
1090 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_sdmmc_set_rate()
1100 			     (div - 1) << CCLK_SDMMC0_DIV_SHIFT);  in rk3562_sdmmc_set_rate()
1107 			     (div - 1) << CCLK_SDMMC1_DIV_SHIFT);  in rk3562_sdmmc_set_rate()
1119 	u32 con, sel, div;  in rk3562_vop_get_rate()  local
1125 		div = (con & ACLK_VOP_DIV_MASK) >> ACLK_VOP_DIV_SHIFT;  in rk3562_vop_get_rate()
1138 		return DIV_TO_RATE(prate, div);  in rk3562_vop_get_rate()
1141 		div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT;  in rk3562_vop_get_rate()
1150 		div = (con & DCLK_VOP1_DIV_MASK) >> DCLK_VOP1_DIV_SHIFT;  in rk3562_vop_get_rate()
1166 	return DIV_TO_RATE(prate, div);  in rk3562_vop_get_rate()
1175 	u32 i, div, sel, best_div = 0, best_sel = 0;  in rk3562_vop_set_rate()  local
1181 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_vop_set_rate()
1184 			div = DIV_ROUND_UP(priv->hpll_hz, rate);  in rk3562_vop_set_rate()
1187 			div = DIV_ROUND_UP(priv->vpll_hz, rate);  in rk3562_vop_set_rate()
1190 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_vop_set_rate()
1196 			     ((div - 1) << ACLK_VOP_DIV_SHIFT));  in rk3562_vop_set_rate()
1200 		div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate);  in rk3562_vop_set_rate()
1204 			     ((div - 1) << DCLK_VOP_DIV_SHIFT));  in rk3562_vop_set_rate()
1206 				      VPLL, div * rate);  in rk3562_vop_set_rate()
1225 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3562_vop_set_rate()
1226 			if (div > 255)  in rk3562_vop_set_rate()
1228 			now = pll_rate / div;  in rk3562_vop_set_rate()
1231 				best_div = div;  in rk3562_vop_set_rate()
1234 			debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",  in rk3562_vop_set_rate()
1257 	u32 con, sel, div;  in rk3562_gmac_get_rate()  local
1285 		div = (con & CLK_GMAC_ETH_OUT2IO_DIV_MASK) >> CLK_GMAC_ETH_OUT2IO_DIV_SHIFT;  in rk3562_gmac_get_rate()
1295 	return DIV_TO_RATE(prate, div);  in rk3562_gmac_get_rate()
1302 	u32 sel, div;  in rk3562_gmac_set_rate()  local
1331 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3562_gmac_set_rate()
1334 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3562_gmac_set_rate()
1340 			     (div - 1) << CLK_GMAC_ETH_OUT2IO_DIV_SHIFT);  in rk3562_gmac_set_rate()