327 	u32 sel, div, mask, shift, con;  in rk3528_cgpll_matrix_get_rate()  local
413 		sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;  in rk3528_cgpll_matrix_get_rate()
414 		if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO  in rk3528_cgpll_matrix_get_rate()
435 	u32 sel, div, mask, shift, con;  in rk3528_cgpll_matrix_set_rate()  local
522 			sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO  in rk3528_cgpll_matrix_set_rate()
525 			sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;  in rk3528_cgpll_matrix_set_rate()
543 		rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);  in rk3528_cgpll_matrix_set_rate()
551 	u32 id, sel, con, mask, shift;  in rk3528_i2c_get_clk()  local
613 	sel = (con & mask) >> shift;  in rk3528_i2c_get_clk()
614 	if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)  in rk3528_i2c_get_clk()
616 	else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)  in rk3528_i2c_get_clk()
618 	else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)  in rk3528_i2c_get_clk()
630 	u32 id, sel, mask, shift;  in rk3528_i2c_set_clk()  local
634 		sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;  in rk3528_i2c_set_clk()
636 		sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;  in rk3528_i2c_set_clk()
638 		sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;  in rk3528_i2c_set_clk()
640 		sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;  in rk3528_i2c_set_clk()
696 		rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);  in rk3528_i2c_set_clk()
698 		rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_i2c_set_clk()
706 	u32 id, sel, con, mask, shift;  in rk3528_spi_get_clk()  local
726 	sel = (con & mask) >> shift;  in rk3528_spi_get_clk()
727 	if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)  in rk3528_spi_get_clk()
729 	else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)  in rk3528_spi_get_clk()
731 	else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)  in rk3528_spi_get_clk()
743 	u32 id, sel, mask, shift;  in rk3528_spi_set_clk()  local
746 		sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;  in rk3528_spi_set_clk()
748 		sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;  in rk3528_spi_set_clk()
750 		sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;  in rk3528_spi_set_clk()
752 		sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;  in rk3528_spi_set_clk()
770 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_spi_set_clk()
778 	u32 id, sel, con, mask, shift;  in rk3528_pwm_get_clk()  local
799 	sel = (con & mask) >> shift;  in rk3528_pwm_get_clk()
800 	if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)  in rk3528_pwm_get_clk()
802 	if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)  in rk3528_pwm_get_clk()
814 	u32 id, sel, mask, shift;  in rk3528_pwm_set_clk()  local
817 		sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;  in rk3528_pwm_set_clk()
819 		sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;  in rk3528_pwm_set_clk()
821 		sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;  in rk3528_pwm_set_clk()
840 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_pwm_set_clk()
909 	u32 div, sel, con;  in rk3528_sdmmc_get_clk()  local
915 	sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>  in rk3528_sdmmc_get_clk()
918 	if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)  in rk3528_sdmmc_get_clk()
920 	else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)  in rk3528_sdmmc_get_clk()
932 	u32 div, sel;  in rk3528_sdmmc_set_clk()  local
936 		sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;  in rk3528_sdmmc_set_clk()
939 		sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;  in rk3528_sdmmc_set_clk()
942 		sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;  in rk3528_sdmmc_set_clk()
949 		     sel << CCLK_SRC_SDMMC0_SEL_SHIFT |  in rk3528_sdmmc_set_clk()
958 	u32 div, sel, con, parent;  in rk3528_sfc_get_clk()  local
963 	sel = (con & SCLK_SFC_SEL_MASK) >>  in rk3528_sfc_get_clk()
965 	if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)  in rk3528_sfc_get_clk()
967 	else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)  in rk3528_sfc_get_clk()
978 	int div, sel;  in rk3528_sfc_set_clk()  local
982 		sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;  in rk3528_sfc_set_clk()
985 		sel = SCLK_SFC_SEL_CLK_CPLL_MUX;  in rk3528_sfc_set_clk()
988 		sel = SCLK_SFC_SEL_CLK_GPLL_MUX;  in rk3528_sfc_set_clk()
995 		     sel << SCLK_SFC_SEL_SHIFT |  in rk3528_sfc_set_clk()
1004 	u32 div, sel, con, parent;  in rk3528_emmc_get_clk()  local
1009 	sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>  in rk3528_emmc_get_clk()
1012 	if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)  in rk3528_emmc_get_clk()
1014 	else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)  in rk3528_emmc_get_clk()
1025 	u32 div, sel;  in rk3528_emmc_set_clk()  local
1029 		sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;  in rk3528_emmc_set_clk()
1032 		sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;  in rk3528_emmc_set_clk()
1035 		sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;  in rk3528_emmc_set_clk()
1042 		     sel << CCLK_SRC_EMMC_SEL_SHIFT |  in rk3528_emmc_set_clk()
1053 	u32 id, con, sel, div;  in rk3528_dclk_vop_get_clk()  local
1080 	sel = (con & sel_mask) >> sel_shift;  in rk3528_dclk_vop_get_clk()
1081 	if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)  in rk3528_dclk_vop_get_clk()
1095 	u32 id, sel, div;  in rk3528_dclk_vop_set_clk()  local
1122 		sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;  in rk3528_dclk_vop_set_clk()
1125 		sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;  in rk3528_dclk_vop_set_clk()
1129 	rk_clrsetreg(&cru->clksel_con[id], sel, div);  in rk3528_dclk_vop_set_clk()
1138 	u32 sel, id, con, frac_div, div;  in rk3528_uart_get_rate()  local
1214 	sel = (con & sel_mask) >> sel_shift;  in rk3528_uart_get_rate()
1216 	if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {  in rk3528_uart_get_rate()
1218 	} else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {  in rk3528_uart_get_rate()
1235 	u32 sel, id, div;  in rk3528_uart_set_rate()  local
1239 		sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;  in rk3528_uart_set_rate()
1242 		sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;  in rk3528_uart_set_rate()
1245 		sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;  in rk3528_uart_set_rate()
1323 	rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);  in rk3528_uart_set_rate()
2024 	u32 id, sel, con, mask, shift;  in rk3528_crypto_get_rate()  local
2045 	sel = (con & mask) >> shift;  in rk3528_crypto_get_rate()
2046 	if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC)  in rk3528_crypto_get_rate()
2048 	else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC)  in rk3528_crypto_get_rate()
2050 	else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC)  in rk3528_crypto_get_rate()
2062 	u32 id, sel, mask, shift;  in rk3528_crypto_set_rate()  local
2065 		sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC;  in rk3528_crypto_set_rate()
2067 		sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC;  in rk3528_crypto_set_rate()
2069 		sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC;  in rk3528_crypto_set_rate()
2071 		sel = CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC;  in rk3528_crypto_set_rate()
2090 	rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);  in rk3528_crypto_set_rate()