415 			prate = priv->gpll_hz;  in rk3528_cgpll_matrix_get_rate()
420 			prate = priv->gpll_hz;  in rk3528_cgpll_matrix_get_rate()
521 		if (priv->gpll_hz % rate == 0) {  in rk3528_cgpll_matrix_set_rate()
523 			prate = priv->gpll_hz;  in rk3528_cgpll_matrix_set_rate()
530 			prate = priv->gpll_hz;  in rk3528_cgpll_matrix_set_rate()
919 		prate = priv->gpll_hz;  in rk3528_sdmmc_get_clk()
941 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3528_sdmmc_set_clk()
966 		parent = priv->gpll_hz;  in rk3528_sfc_get_clk()
987 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3528_sfc_set_clk()
1013 		parent = priv->gpll_hz;  in rk3528_emmc_get_clk()
1034 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3528_emmc_set_clk()
1082 		prate = priv->gpll_hz;  in rk3528_dclk_vop_get_clk()
1120 	if ((priv->gpll_hz % rate) == 0) {  in rk3528_dclk_vop_set_clk()
1121 		prate = priv->gpll_hz;  in rk3528_dclk_vop_set_clk()
1217 		rate = DIV_TO_RATE(priv->gpll_hz, div);  in rk3528_uart_get_rate()
1222 		rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;  in rk3528_uart_get_rate()
1241 	} else if (priv->gpll_hz % rate == 0) {  in rk3528_uart_set_rate()
1243 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3528_uart_set_rate()
1247 		rational_best_approximation(rate, priv->gpll_hz / div,  in rk3528_uart_set_rate()
1337 	if (!priv->gpll_hz || !priv->cpll_hz) {  in rk3528_clk_get_rate()
1339 		       __func__, priv->gpll_hz, priv->cpll_hz);  in rk3528_clk_get_rate()
1456 	if (!priv->gpll_hz) {  in rk3528_clk_set_rate()
1457 		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);  in rk3528_clk_set_rate()
1477 		priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],  in rk3528_clk_set_rate()
1899 	if (priv->gpll_hz != GPLL_HZ) {  in rk3528_clk_init()
1903 			priv->gpll_hz = GPLL_HZ;  in rk3528_clk_init()