Lines Matching refs:cpll_hz
417 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
422 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
526 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
532 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
921 prate = priv->cpll_hz; in rk3528_sdmmc_get_clk()
937 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sdmmc_set_clk()
938 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sdmmc_set_clk()
968 parent = priv->cpll_hz; in rk3528_sfc_get_clk()
983 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sfc_set_clk()
984 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sfc_set_clk()
1015 parent = priv->cpll_hz; in rk3528_emmc_get_clk()
1030 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_emmc_set_clk()
1031 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_emmc_set_clk()
1084 prate = priv->cpll_hz; in rk3528_dclk_vop_get_clk()
1124 prate = priv->cpll_hz; in rk3528_dclk_vop_set_clk()
1337 if (!priv->gpll_hz || !priv->cpll_hz) { in rk3528_clk_get_rate()
1339 __func__, priv->gpll_hz, priv->cpll_hz); in rk3528_clk_get_rate()
1471 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], in rk3528_clk_set_rate()
1892 if (priv->cpll_hz != CPLL_HZ) { in rk3528_clk_init()
1896 priv->cpll_hz = CPLL_HZ; in rk3528_clk_init()