Lines Matching full:rate
84 .rate = _rate##U, \
197 const struct rockchip_cpu_rate_table *rate; in rk3528_armclk_set_clk() local
201 rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate); in rk3528_armclk_set_clk()
202 if (!rate) { in rk3528_armclk_set_clk()
203 printf("%s unsupported rate\n", __func__); in rk3528_armclk_set_clk()
217 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
220 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
223 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
226 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
279 ulong clk_id, ulong rate) in rk3528_ppll_matrix_set_rate() argument
314 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3528_ppll_matrix_set_rate()
432 ulong clk_id, ulong rate) in rk3528_cgpll_matrix_set_rate() argument
521 if (priv->gpll_hz % rate == 0) { in rk3528_cgpll_matrix_set_rate()
537 div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1; in rk3528_cgpll_matrix_set_rate()
539 div = DIV_ROUND_UP(prate, rate); in rk3528_cgpll_matrix_set_rate()
553 ulong rate; in rk3528_i2c_get_clk() local
615 rate = 200 * MHz; in rk3528_i2c_get_clk()
617 rate = 100 * MHz; in rk3528_i2c_get_clk()
619 rate = 50 * MHz; in rk3528_i2c_get_clk()
621 rate = OSC_HZ; in rk3528_i2c_get_clk()
623 return rate; in rk3528_i2c_get_clk()
627 ulong rate) in rk3528_i2c_set_clk() argument
633 if (rate == 200 * MHz) in rk3528_i2c_set_clk()
635 else if (rate == 100 * MHz) in rk3528_i2c_set_clk()
637 else if (rate == 50 * MHz) in rk3528_i2c_set_clk()
707 ulong rate; in rk3528_spi_get_clk() local
728 rate = 200 * MHz; in rk3528_spi_get_clk()
730 rate = 100 * MHz; in rk3528_spi_get_clk()
732 rate = 50 * MHz; in rk3528_spi_get_clk()
734 rate = OSC_HZ; in rk3528_spi_get_clk()
736 return rate; in rk3528_spi_get_clk()
740 ulong clk_id, ulong rate) in rk3528_spi_set_clk() argument
745 if (rate == 200 * MHz) in rk3528_spi_set_clk()
747 else if (rate == 100 * MHz) in rk3528_spi_set_clk()
749 else if (rate == 50 * MHz) in rk3528_spi_set_clk()
779 ulong rate; in rk3528_pwm_get_clk() local
801 rate = 100 * MHz; in rk3528_pwm_get_clk()
803 rate = 50 * MHz; in rk3528_pwm_get_clk()
805 rate = OSC_HZ; in rk3528_pwm_get_clk()
807 return rate; in rk3528_pwm_get_clk()
811 ulong clk_id, ulong rate) in rk3528_pwm_set_clk() argument
816 if (rate == 100 * MHz) in rk3528_pwm_set_clk()
818 else if (rate == 50 * MHz) in rk3528_pwm_set_clk()
875 ulong clk_id, ulong rate) in rk3528_adc_set_clk() argument
900 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_adc_set_clk()
929 ulong clk_id, ulong rate) in rk3528_sdmmc_set_clk() argument
934 if (OSC_HZ % rate == 0) { in rk3528_sdmmc_set_clk()
935 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_sdmmc_set_clk()
937 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sdmmc_set_clk()
938 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sdmmc_set_clk()
941 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sdmmc_set_clk()
975 static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate) in rk3528_sfc_set_clk() argument
980 if (OSC_HZ % rate == 0) { in rk3528_sfc_set_clk()
981 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_sfc_set_clk()
983 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sfc_set_clk()
984 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sfc_set_clk()
987 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sfc_set_clk()
1022 static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate) in rk3528_emmc_set_clk() argument
1027 if (OSC_HZ % rate == 0) { in rk3528_emmc_set_clk()
1028 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_emmc_set_clk()
1030 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_emmc_set_clk()
1031 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_emmc_set_clk()
1034 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_emmc_set_clk()
1090 ulong clk_id, ulong rate) in rk3528_dclk_vop_set_clk() argument
1120 if ((priv->gpll_hz % rate) == 0) { in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1139 ulong m, n, rate; in rk3528_uart_get_rate() local
1217 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3528_uart_get_rate()
1222 rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m; in rk3528_uart_get_rate()
1224 rate = OSC_HZ; in rk3528_uart_get_rate()
1227 return rate; in rk3528_uart_get_rate()
1231 ulong clk_id, ulong rate) in rk3528_uart_set_rate() argument
1238 if (rate == OSC_HZ) { in rk3528_uart_set_rate()
1240 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_uart_set_rate()
1241 } else if (priv->gpll_hz % rate == 0) { in rk3528_uart_set_rate()
1243 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_uart_set_rate()
1247 rational_best_approximation(rate, priv->gpll_hz / div, in rk3528_uart_set_rate()
1335 ulong rate = 0; in rk3528_clk_get_rate() local
1346 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, in rk3528_clk_get_rate()
1350 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_get_rate()
1354 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_get_rate()
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1363 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, in rk3528_clk_get_rate()
1368 rate = OSC_HZ; in rk3528_clk_get_rate()
1378 rate = rk3528_i2c_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1382 rate = rk3528_spi_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1386 rate = rk3528_pwm_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1391 rate = rk3528_adc_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1394 rate = rk3528_emmc_get_clk(priv); in rk3528_clk_get_rate()
1398 rate = rk3528_sdmmc_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1401 rate = rk3528_sfc_get_clk(priv); in rk3528_clk_get_rate()
1405 rate = rk3528_dclk_vop_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1408 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4; in rk3528_clk_get_rate()
1411 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1); in rk3528_clk_get_rate()
1421 rate = rk3528_uart_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1434 rate = rk3528_cgpll_matrix_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1442 rate = rk3528_ppll_matrix_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1448 return rate; in rk3528_clk_get_rate()
1451 static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) in rk3528_clk_set_rate() argument
1465 rk3528_armclk_set_clk(priv, rate); in rk3528_clk_set_rate()
1466 priv->armclk_hz = rate; in rk3528_clk_set_rate()
1470 CPLL, rate); in rk3528_clk_set_rate()
1476 GPLL, rate); in rk3528_clk_set_rate()
1482 PPLL, rate); in rk3528_clk_set_rate()
1487 return (rate == OSC_HZ) ? 0 : -EINVAL; in rk3528_clk_set_rate()
1496 ret = rk3528_i2c_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1500 ret = rk3528_spi_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1504 ret = rk3528_pwm_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1509 ret = rk3528_adc_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1513 ret = rk3528_sdmmc_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1516 ret = rk3528_sfc_set_clk(priv, rate); in rk3528_clk_set_rate()
1519 ret = rk3528_emmc_set_clk(priv, rate); in rk3528_clk_set_rate()
1523 ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1533 ret = rk3528_uart_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1546 ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1552 ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1601 ulong rate = 0; in rk3528_grfclk_get_rate() local
1615 rate = rk3528_sdmmc_get_clk(priv, CCLK_SRC_SDMMC0) / 2; in rk3528_grfclk_get_rate()
1621 return rate; in rk3528_grfclk_get_rate()
1640 ulong rate; in rk3528_mmc_get_phase() local
1642 rate = rk3528_grfclk_get_rate(clk); in rk3528_mmc_get_phase()
1643 if (rate < 0) in rk3528_mmc_get_phase()
1644 return rate; in rk3528_mmc_get_phase()
1657 36 * (rate / 1000000); in rk3528_mmc_get_phase()
1672 ulong rate; in rk3528_mmc_set_phase() local
1674 rate = rk3528_grfclk_get_rate(clk); in rk3528_mmc_set_phase()
1675 if (rate < 0) in rk3528_mmc_set_phase()
1676 return rate; in rk3528_mmc_set_phase()
1687 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3528_mmc_set_phase()
1760 ulong rate; in soc_clk_dump() local
1786 rate = clk_get_rate(&clk); in soc_clk_dump()
1789 if (rate < 0) in soc_clk_dump()
1794 rate / 1000); in soc_clk_dump()
1796 if (rate < 0) in soc_clk_dump()
1801 rate / 1000); in soc_clk_dump()
1847 * |-- clk_matrix_200m_src_div=1 => rate: 300M in rk3528_clk_init()
1848 * |-- clk_matrix_300m_src_div=2 => rate: 200M in rk3528_clk_init()
1850 * Avoid overclocking when change GPLL rate: in rk3528_clk_init()
1927 /* The default rate is 100Mhz, it's not friendly for remote IR module */ in rk3528_clk_init()
2025 ulong rate; in rk3528_crypto_get_rate() local
2047 rate = 300 * MHz; in rk3528_crypto_get_rate()
2049 rate = 200 * MHz; in rk3528_crypto_get_rate()
2051 rate = 100 * MHz; in rk3528_crypto_get_rate()
2053 rate = OSC_HZ; in rk3528_crypto_get_rate()
2055 return rate; in rk3528_crypto_get_rate()
2059 struct clk *clk, ulong rate) in rk3528_crypto_set_rate() argument
2064 if (rate == 300 * MHz) in rk3528_crypto_set_rate()
2066 else if (rate == 200 * MHz) in rk3528_crypto_set_rate()
2068 else if (rate == 100 * MHz) in rk3528_crypto_set_rate()
2108 static ulong rk3528_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3528_clk_scmi_set_rate() argument
2115 return rk3528_crypto_set_rate(priv, clk, rate); in rk3528_clk_scmi_set_rate()