Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Joseph Chen <chenjh@rock-chips.com>
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3528-cru.h>
21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
27 * - frac mode: refdiv can be 1 or 2 only
28 * - int mode: refdiv has no special limit
29 * - VCO range: [950, 3800] MHZ
32 * - int mode: refdiv can be 1 or 2 only
33 * - VCO range: [475, 1900] MHZ
89 /* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
147 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
198 struct rk3528_cru *cru = priv->cru; in rk3528_armclk_set_clk()
204 return -EINVAL; in rk3528_armclk_set_clk()
210 old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL); in rk3528_armclk_set_clk()
213 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
214 return -EINVAL; in rk3528_armclk_set_clk()
216 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, in rk3528_armclk_set_clk()
217 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
219 rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK, in rk3528_armclk_set_clk()
220 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
222 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, in rk3528_armclk_set_clk()
223 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
225 rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK, in rk3528_armclk_set_clk()
226 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
229 priv->cru, APLL, new_rate)) in rk3528_armclk_set_clk()
230 return -EINVAL; in rk3528_armclk_set_clk()
239 struct rk3528_cru *cru = priv->cru; in rk3528_ppll_matrix_get_rate()
240 u32 div, mask, shift; in rk3528_ppll_matrix_get_rate() local
248 reg = &cru->pcieclksel_con[1]; in rk3528_ppll_matrix_get_rate()
254 reg = &cru->pcieclksel_con[1]; in rk3528_ppll_matrix_get_rate()
261 reg = &cru->clksel_con[60]; in rk3528_ppll_matrix_get_rate()
267 reg = &cru->clksel_con[60]; in rk3528_ppll_matrix_get_rate()
270 return -ENOENT; in rk3528_ppll_matrix_get_rate()
273 div = (readl(reg) & mask) >> shift; in rk3528_ppll_matrix_get_rate()
275 return DIV_TO_RATE(priv->ppll_hz, div); in rk3528_ppll_matrix_get_rate()
281 struct rk3528_cru *cru = priv->cru; in rk3528_ppll_matrix_set_rate()
282 u32 id, div, mask, shift; in rk3528_ppll_matrix_set_rate() local
311 return -ENOENT; in rk3528_ppll_matrix_set_rate()
314 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3528_ppll_matrix_set_rate()
316 rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift); in rk3528_ppll_matrix_set_rate()
318 rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift); in rk3528_ppll_matrix_set_rate()
326 struct rk3528_cru *cru = priv->cru; in rk3528_cgpll_matrix_get_rate()
327 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_get_rate() local
409 return -ENOENT; in rk3528_cgpll_matrix_get_rate()
413 sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift; in rk3528_cgpll_matrix_get_rate()
415 prate = priv->gpll_hz; in rk3528_cgpll_matrix_get_rate()
417 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
420 prate = priv->gpll_hz; in rk3528_cgpll_matrix_get_rate()
422 prate = priv->cpll_hz; in rk3528_cgpll_matrix_get_rate()
425 div = (readl(&cru->clksel_con[con]) & mask) >> shift; in rk3528_cgpll_matrix_get_rate()
427 /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */ in rk3528_cgpll_matrix_get_rate()
428 return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div); in rk3528_cgpll_matrix_get_rate()
434 struct rk3528_cru *cru = priv->cru; in rk3528_cgpll_matrix_set_rate()
435 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_set_rate() local
517 return -ENOENT; in rk3528_cgpll_matrix_set_rate()
521 if (priv->gpll_hz % rate == 0) { in rk3528_cgpll_matrix_set_rate()
523 prate = priv->gpll_hz; in rk3528_cgpll_matrix_set_rate()
526 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
530 prate = priv->gpll_hz; in rk3528_cgpll_matrix_set_rate()
532 prate = priv->cpll_hz; in rk3528_cgpll_matrix_set_rate()
536 /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */ in rk3528_cgpll_matrix_set_rate()
537 div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1; in rk3528_cgpll_matrix_set_rate()
539 div = DIV_ROUND_UP(prate, rate); in rk3528_cgpll_matrix_set_rate()
541 rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift); in rk3528_cgpll_matrix_set_rate()
543 rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift); in rk3528_cgpll_matrix_set_rate()
550 struct rk3528_cru *cru = priv->cru; in rk3528_i2c_get_clk()
606 return -ENOENT; in rk3528_i2c_get_clk()
610 con = readl(&cru->pmuclksel_con[id]); in rk3528_i2c_get_clk()
612 con = readl(&cru->clksel_con[id]); in rk3528_i2c_get_clk()
629 struct rk3528_cru *cru = priv->cru; in rk3528_i2c_set_clk()
692 return -ENOENT; in rk3528_i2c_set_clk()
696 rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift); in rk3528_i2c_set_clk()
698 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); in rk3528_i2c_set_clk()
705 struct rk3528_cru *cru = priv->cru; in rk3528_spi_get_clk()
722 return -ENOENT; in rk3528_spi_get_clk()
725 con = readl(&cru->clksel_con[id]); in rk3528_spi_get_clk()
742 struct rk3528_cru *cru = priv->cru; in rk3528_spi_set_clk()
767 return -ENOENT; in rk3528_spi_set_clk()
770 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); in rk3528_spi_set_clk()
777 struct rk3528_cru *cru = priv->cru; in rk3528_pwm_get_clk()
795 return -ENOENT; in rk3528_pwm_get_clk()
798 con = readl(&cru->clksel_con[id]); in rk3528_pwm_get_clk()
813 struct rk3528_cru *cru = priv->cru; in rk3528_pwm_set_clk()
837 return -ENOENT; in rk3528_pwm_set_clk()
840 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); in rk3528_pwm_set_clk()
847 struct rk3528_cru *cru = priv->cru; in rk3528_adc_get_clk()
848 u32 div, con; in rk3528_adc_get_clk() local
850 con = readl(&cru->clksel_con[74]); in rk3528_adc_get_clk()
853 div = (con & CLK_SARADC_DIV_MASK) >> in rk3528_adc_get_clk()
858 div = (con & CLK_TSADC_TSEN_DIV_MASK) >> in rk3528_adc_get_clk()
863 div = (con & CLK_TSADC_DIV_MASK) >> in rk3528_adc_get_clk()
868 return -ENOENT; in rk3528_adc_get_clk()
871 return DIV_TO_RATE(OSC_HZ, div); in rk3528_adc_get_clk()
877 struct rk3528_cru *cru = priv->cru; in rk3528_adc_set_clk()
878 u32 div, mask, shift; in rk3528_adc_set_clk() local
897 return -ENOENT; in rk3528_adc_set_clk()
900 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_adc_set_clk()
901 rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift); in rk3528_adc_set_clk()
908 struct rk3528_cru *cru = priv->cru; in rk3528_sdmmc_get_clk()
909 u32 div, sel, con; in rk3528_sdmmc_get_clk() local
912 con = readl(&cru->clksel_con[85]); in rk3528_sdmmc_get_clk()
913 div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >> in rk3528_sdmmc_get_clk()
919 prate = priv->gpll_hz; in rk3528_sdmmc_get_clk()
921 prate = priv->cpll_hz; in rk3528_sdmmc_get_clk()
925 return DIV_TO_RATE(prate, div); in rk3528_sdmmc_get_clk()
931 struct rk3528_cru *cru = priv->cru; in rk3528_sdmmc_set_clk()
932 u32 div, sel; in rk3528_sdmmc_set_clk() local
935 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_sdmmc_set_clk()
937 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sdmmc_set_clk()
938 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sdmmc_set_clk()
941 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sdmmc_set_clk()
945 assert(div - 1 <= 31); in rk3528_sdmmc_set_clk()
946 rk_clrsetreg(&cru->clksel_con[85], in rk3528_sdmmc_set_clk()
950 (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT); in rk3528_sdmmc_set_clk()
957 struct rk3528_cru *cru = priv->cru; in rk3528_sfc_get_clk()
958 u32 div, sel, con, parent; in rk3528_sfc_get_clk() local
960 con = readl(&cru->clksel_con[61]); in rk3528_sfc_get_clk()
961 div = (con & SCLK_SFC_DIV_MASK) >> in rk3528_sfc_get_clk()
966 parent = priv->gpll_hz; in rk3528_sfc_get_clk()
968 parent = priv->cpll_hz; in rk3528_sfc_get_clk()
972 return DIV_TO_RATE(parent, div); in rk3528_sfc_get_clk()
977 struct rk3528_cru *cru = priv->cru; in rk3528_sfc_set_clk()
978 int div, sel; in rk3528_sfc_set_clk() local
981 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_sfc_set_clk()
983 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_sfc_set_clk()
984 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_sfc_set_clk()
987 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_sfc_set_clk()
991 assert(div - 1 <= 63); in rk3528_sfc_set_clk()
992 rk_clrsetreg(&cru->clksel_con[61], in rk3528_sfc_set_clk()
996 (div - 1) << SCLK_SFC_DIV_SHIFT); in rk3528_sfc_set_clk()
1003 struct rk3528_cru *cru = priv->cru; in rk3528_emmc_get_clk()
1004 u32 div, sel, con, parent; in rk3528_emmc_get_clk() local
1006 con = readl(&cru->clksel_con[62]); in rk3528_emmc_get_clk()
1007 div = (con & CCLK_SRC_EMMC_DIV_MASK) >> in rk3528_emmc_get_clk()
1013 parent = priv->gpll_hz; in rk3528_emmc_get_clk()
1015 parent = priv->cpll_hz; in rk3528_emmc_get_clk()
1019 return DIV_TO_RATE(parent, div); in rk3528_emmc_get_clk()
1024 struct rk3528_cru *cru = priv->cru; in rk3528_emmc_set_clk()
1025 u32 div, sel; in rk3528_emmc_set_clk() local
1028 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_emmc_set_clk()
1030 } else if ((priv->cpll_hz % rate) == 0) { in rk3528_emmc_set_clk()
1031 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3528_emmc_set_clk()
1034 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_emmc_set_clk()
1038 assert(div - 1 <= 31); in rk3528_emmc_set_clk()
1039 rk_clrsetreg(&cru->clksel_con[62], in rk3528_emmc_set_clk()
1043 (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT); in rk3528_emmc_set_clk()
1050 struct rk3528_cru *cru = priv->cru; in rk3528_dclk_vop_get_clk()
1053 u32 id, con, sel, div; in rk3528_dclk_vop_get_clk() local
1075 return -ENOENT; in rk3528_dclk_vop_get_clk()
1078 con = readl(&cru->clksel_con[id]); in rk3528_dclk_vop_get_clk()
1079 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1082 prate = priv->gpll_hz; in rk3528_dclk_vop_get_clk()
1084 prate = priv->cpll_hz; in rk3528_dclk_vop_get_clk()
1086 return DIV_TO_RATE(prate, div); in rk3528_dclk_vop_get_clk()
1092 struct rk3528_cru *cru = priv->cru; in rk3528_dclk_vop_set_clk()
1095 u32 id, sel, div; in rk3528_dclk_vop_set_clk() local
1117 return -ENOENT; in rk3528_dclk_vop_set_clk()
1120 if ((priv->gpll_hz % rate) == 0) { in rk3528_dclk_vop_set_clk()
1121 prate = priv->gpll_hz; in rk3528_dclk_vop_set_clk()
1124 prate = priv->cpll_hz; in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1129 rk_clrsetreg(&cru->clksel_con[id], sel, div); in rk3528_dclk_vop_set_clk()
1136 struct rk3528_cru *cru = priv->cru; in rk3528_uart_get_rate()
1138 u32 sel, id, con, frac_div, div; in rk3528_uart_get_rate() local
1207 return -ENOENT; in rk3528_uart_get_rate()
1210 con = readl(&cru->clksel_con[id - 2]); in rk3528_uart_get_rate()
1211 div = (con & div_mask) >> div_shift; in rk3528_uart_get_rate()
1213 con = readl(&cru->clksel_con[id]); in rk3528_uart_get_rate()
1217 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3528_uart_get_rate()
1219 frac_div = readl(&cru->clksel_con[id - 1]); in rk3528_uart_get_rate()
1222 rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m; in rk3528_uart_get_rate()
1233 struct rk3528_cru *cru = priv->cru; in rk3528_uart_set_rate()
1235 u32 sel, id, div; in rk3528_uart_set_rate() local
1240 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3528_uart_set_rate()
1241 } else if (priv->gpll_hz % rate == 0) { in rk3528_uart_set_rate()
1243 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3528_uart_set_rate()
1246 div = 2; in rk3528_uart_set_rate()
1247 rational_best_approximation(rate, priv->gpll_hz / div, in rk3528_uart_set_rate()
1248 GENMASK(16 - 1, 0), in rk3528_uart_set_rate()
1249 GENMASK(16 - 1, 0), in rk3528_uart_set_rate()
1319 return -ENOENT; in rk3528_uart_set_rate()
1322 rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift); in rk3528_uart_set_rate()
1323 rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift); in rk3528_uart_set_rate()
1326 writel(val, &cru->clksel_con[id - 1]); in rk3528_uart_set_rate()
1332 static ulong rk3528_clk_get_rate(struct clk *clk) in rk3528_clk_get_rate() argument
1334 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_clk_get_rate()
1337 if (!priv->gpll_hz || !priv->cpll_hz) { in rk3528_clk_get_rate()
1339 __func__, priv->gpll_hz, priv->cpll_hz); in rk3528_clk_get_rate()
1340 return -ENOENT; in rk3528_clk_get_rate()
1343 switch (clk->id) { in rk3528_clk_get_rate()
1346 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, in rk3528_clk_get_rate()
1350 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_get_rate()
1354 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_get_rate()
1359 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_get_rate()
1363 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, in rk3528_clk_get_rate()
1378 rate = rk3528_i2c_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1382 rate = rk3528_spi_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1386 rate = rk3528_pwm_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1391 rate = rk3528_adc_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1398 rate = rk3528_sdmmc_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1405 rate = rk3528_dclk_vop_get_clk(priv, clk->id); in rk3528_clk_get_rate()
1421 rate = rk3528_uart_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1434 rate = rk3528_cgpll_matrix_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1442 rate = rk3528_ppll_matrix_get_rate(priv, clk->id); in rk3528_clk_get_rate()
1445 return -ENOENT; in rk3528_clk_get_rate()
1451 static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) in rk3528_clk_set_rate() argument
1453 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_clk_set_rate()
1456 if (!priv->gpll_hz) { in rk3528_clk_set_rate()
1457 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rk3528_clk_set_rate()
1458 return -ENOENT; in rk3528_clk_set_rate()
1461 switch (clk->id) { in rk3528_clk_set_rate()
1464 if (priv->armclk_hz) in rk3528_clk_set_rate()
1466 priv->armclk_hz = rate; in rk3528_clk_set_rate()
1469 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_set_rate()
1471 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], in rk3528_clk_set_rate()
1472 priv->cru, CPLL); in rk3528_clk_set_rate()
1475 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_set_rate()
1477 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], in rk3528_clk_set_rate()
1478 priv->cru, GPLL); in rk3528_clk_set_rate()
1481 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_set_rate()
1483 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], in rk3528_clk_set_rate()
1484 priv->cru, PPLL); in rk3528_clk_set_rate()
1487 return (rate == OSC_HZ) ? 0 : -EINVAL; in rk3528_clk_set_rate()
1496 ret = rk3528_i2c_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1500 ret = rk3528_spi_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1504 ret = rk3528_pwm_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1509 ret = rk3528_adc_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1513 ret = rk3528_sdmmc_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1523 ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate); in rk3528_clk_set_rate()
1533 ret = rk3528_uart_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1546 ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1552 ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate); in rk3528_clk_set_rate()
1557 ret = rk3528_ppll_matrix_get_rate(priv, clk->id); in rk3528_clk_set_rate()
1560 return -ENOENT; in rk3528_clk_set_rate()
1567 static int rk3528_clk_set_parent(struct clk *clk, struct clk *parent) in rk3528_clk_set_parent() argument
1569 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_clk_set_parent()
1570 const char *clock_dev_name = parent->dev->name; in rk3528_clk_set_parent()
1572 switch (clk->id) { in rk3528_clk_set_parent()
1576 rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 1); in rk3528_clk_set_parent()
1578 rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 0); in rk3528_clk_set_parent()
1582 return -ENOENT; in rk3528_clk_set_parent()
1597 static ulong rk3528_grfclk_get_rate(struct clk *clk) in rk3528_grfclk_get_rate() argument
1613 switch (clk->id) { in rk3528_grfclk_get_rate()
1618 return -ENOENT; in rk3528_grfclk_get_rate()
1630 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1635 int rk3528_mmc_get_phase(struct clk *clk) in rk3528_mmc_get_phase() argument
1637 struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_mmc_get_phase()
1642 rate = rk3528_grfclk_get_rate(clk); in rk3528_mmc_get_phase()
1646 if (clk->id == SCLK_SDMMC_SAMPLE) in rk3528_mmc_get_phase()
1647 raw_value = readl(&priv->grf->sdmmc_con1); in rk3528_mmc_get_phase()
1649 return -ENONET; in rk3528_mmc_get_phase()
1667 int rk3528_mmc_set_phase(struct clk *clk, u32 degrees) in rk3528_mmc_set_phase() argument
1669 struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_mmc_set_phase()
1674 rate = rk3528_grfclk_get_rate(clk); in rk3528_mmc_set_phase()
1683 * don't overflow 32-bit / 64-bit numbers. in rk3528_mmc_set_phase()
1697 if (clk->id == SCLK_SDMMC_SAMPLE) in rk3528_mmc_set_phase()
1698 writel(raw_value | 0xffff0000, &priv->grf->sdmmc_con1); in rk3528_mmc_set_phase()
1700 return -ENONET; in rk3528_mmc_set_phase()
1703 degrees, delay_num, raw_value, rk3528_mmc_get_phase(clk)); in rk3528_mmc_set_phase()
1708 static int rk3528_grfclk_get_phase(struct clk *clk) in rk3528_grfclk_get_phase() argument
1712 debug("%s %ld\n", __func__, clk->id); in rk3528_grfclk_get_phase()
1713 switch (clk->id) { in rk3528_grfclk_get_phase()
1715 ret = rk3528_mmc_get_phase(clk); in rk3528_grfclk_get_phase()
1718 return -ENOENT; in rk3528_grfclk_get_phase()
1724 static int rk3528_grfclk_set_phase(struct clk *clk, int degrees) in rk3528_grfclk_set_phase() argument
1728 debug("%s %ld\n", __func__, clk->id); in rk3528_grfclk_set_phase()
1729 switch (clk->id) { in rk3528_grfclk_set_phase()
1731 ret = rk3528_mmc_set_phase(clk, degrees); in rk3528_grfclk_set_phase()
1734 return -ENOENT; in rk3528_grfclk_set_phase()
1748 * soc_clk_dump() - Print clock frequencies
1751 * Implementation for the clk dump command.
1758 struct clk clk; in soc_clk_dump() local
1772 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1773 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1774 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1775 priv->armclk_init_hz / 1000, in soc_clk_dump()
1776 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1777 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1780 if (clk_dump->name) { in soc_clk_dump()
1781 clk.id = clk_dump->id; in soc_clk_dump()
1782 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1786 rate = clk_get_rate(&clk); in soc_clk_dump()
1787 clk_free(&clk); in soc_clk_dump()
1790 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1793 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1797 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1800 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1814 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3528_grfclk_probe()
1815 if (IS_ERR(priv->grf)) in rk3528_grfclk_probe()
1816 return PTR_ERR(priv->grf); in rk3528_grfclk_probe()
1822 { .compatible = "rockchip,rk3528-grf-cru" },
1839 priv->sync_kernel = false; in rk3528_clk_init()
1847 * |-- clk_matrix_200m_src_div=1 => rate: 300M in rk3528_clk_init()
1848 * |-- clk_matrix_300m_src_div=2 => rate: 200M in rk3528_clk_init()
1854 writel(0x01200120, &priv->cru->clksel_con[1]); in rk3528_clk_init()
1855 writel(0x00030003, &priv->cru->clksel_con[2]); in rk3528_clk_init()
1857 if (!priv->armclk_enter_hz) { in rk3528_clk_init()
1858 priv->armclk_enter_hz = in rk3528_clk_init()
1860 priv->cru, APLL); in rk3528_clk_init()
1861 priv->armclk_init_hz = priv->armclk_enter_hz; in rk3528_clk_init()
1864 if (priv->armclk_init_hz != APLL_HZ) { in rk3528_clk_init()
1867 priv->armclk_init_hz = APLL_HZ; in rk3528_clk_init()
1870 if (!priv->armclk_enter_hz) { in rk3528_clk_init()
1871 struct clk clk; in rk3528_clk_init() local
1873 ret = rockchip_get_scmi_clk(&clk.dev); in rk3528_clk_init()
1875 printf("Failed to get scmi clk dev\n"); in rk3528_clk_init()
1879 clk.id = SCMI_CLK_CPU; in rk3528_clk_init()
1880 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); in rk3528_clk_init()
1885 priv->armclk_enter_hz = in rk3528_clk_init()
1887 priv->cru, APLL); in rk3528_clk_init()
1888 priv->armclk_init_hz = CPU_PVTPLL_HZ; in rk3528_clk_init()
1892 if (priv->cpll_hz != CPLL_HZ) { in rk3528_clk_init()
1893 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_init()
1896 priv->cpll_hz = CPLL_HZ; in rk3528_clk_init()
1899 if (priv->gpll_hz != GPLL_HZ) { in rk3528_clk_init()
1900 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, in rk3528_clk_init()
1903 priv->gpll_hz = GPLL_HZ; in rk3528_clk_init()
1906 if (priv->ppll_hz != PPLL_HZ) { in rk3528_clk_init()
1907 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, in rk3528_clk_init()
1910 priv->ppll_hz = PPLL_HZ; in rk3528_clk_init()
1939 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3528_clk_probe()
1940 if (IS_ERR(priv->grf)) in rk3528_clk_probe()
1941 return PTR_ERR(priv->grf); in rk3528_clk_probe()
1947 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk3528_clk_probe()
1952 priv->sync_kernel = true; in rk3528_clk_probe()
1961 priv->cru = dev_read_addr_ptr(dev); in rk3528_clk_ofdata_to_platdata()
1980 priv->glb_srst_fst_value = offsetof(struct rk3528_cru, in rk3528_clk_bind()
1982 priv->glb_srst_snd_value = offsetof(struct rk3528_cru, in rk3528_clk_bind()
1984 sys_child->priv = priv; in rk3528_clk_bind()
1993 sf_priv->sf_reset_offset = offsetof(struct rk3528_cru, in rk3528_clk_bind()
1995 sf_priv->sf_reset_num = 47; in rk3528_clk_bind()
1996 sf_child->priv = sf_priv; in rk3528_clk_bind()
2003 { .compatible = "rockchip,rk3528-cru" },
2018 /* spl scmi clk */
2021 static ulong rk3528_crypto_get_rate(struct rk3528_clk_priv *priv, struct clk *clk) in rk3528_crypto_get_rate() argument
2023 struct rk3528_cru *cru = priv->cru; in rk3528_crypto_get_rate()
2027 switch (clk->id) { in rk3528_crypto_get_rate()
2041 return -ENOENT; in rk3528_crypto_get_rate()
2044 con = readl(&cru->clksel_con[id]); in rk3528_crypto_get_rate()
2059 struct clk *clk, ulong rate) in rk3528_crypto_set_rate() argument
2061 struct rk3528_cru *cru = priv->cru; in rk3528_crypto_set_rate()
2073 switch (clk->id) { in rk3528_crypto_set_rate()
2087 return -ENOENT; in rk3528_crypto_set_rate()
2090 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); in rk3528_crypto_set_rate()
2092 return rk3528_crypto_get_rate(priv, clk); in rk3528_crypto_set_rate()
2095 static ulong rk3528_clk_scmi_get_rate(struct clk *clk) in rk3528_clk_scmi_get_rate() argument
2097 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_clk_scmi_get_rate()
2099 switch (clk->id) { in rk3528_clk_scmi_get_rate()
2102 return rk3528_crypto_get_rate(priv, clk); in rk3528_clk_scmi_get_rate()
2104 return -ENOENT; in rk3528_clk_scmi_get_rate()
2108 static ulong rk3528_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3528_clk_scmi_set_rate() argument
2110 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); in rk3528_clk_scmi_set_rate()
2112 switch (clk->id) { in rk3528_clk_scmi_set_rate()
2115 return rk3528_crypto_set_rate(priv, clk, rate); in rk3528_clk_scmi_set_rate()
2117 return -ENOENT; in rk3528_clk_scmi_set_rate()
2127 priv->cru = (struct rk3528_cru *)0xff4a0000; in rk3528_scmi_clk_ofdata_to_platdata()