38 	u32 postdiv1;  member
51 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
344 	u32 refdiv, fbdiv, postdiv1, postdiv2;  in rkclk_pll_get_rate()  local
356 		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;  in rkclk_pll_get_rate()
359 		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;  in rkclk_pll_get_rate()
370 	u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;  in rkclk_set_pll()
374 			   pll_con, div->fbdiv, div->refdiv, div->postdiv1,  in rkclk_set_pll()
397 		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) |  in rkclk_set_pll()
448 	u32 postdiv1, postdiv2 = 1;  in pll_para_config()  local
461 	postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);  in pll_para_config()
462 	if (postdiv1 > max_postdiv1) {  in pll_para_config()
463 		postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);  in pll_para_config()
464 		postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);  in pll_para_config()
467 	vco_khz = freq_khz * postdiv1 * postdiv2;  in pll_para_config()
476 	div->postdiv1 = postdiv1;  in pll_para_config()
924 		{.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};  in rk3399_ddr_set_clk()
928 		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};  in rk3399_ddr_set_clk()
932 		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};  in rk3399_ddr_set_clk()
936 		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};  in rk3399_ddr_set_clk()
940 		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};  in rk3399_ddr_set_clk()
944 		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};  in rk3399_ddr_set_clk()
948 		{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};  in rk3399_ddr_set_clk()