342 static uint32_t rkclk_pll_get_rate(u32 *pll_con)  in rkclk_pll_get_rate()  argument
347 	con = readl(&pll_con[3]);  in rkclk_pll_get_rate()
353 		con = readl(&pll_con[0]);  in rkclk_pll_get_rate()
355 		con = readl(&pll_con[1]);  in rkclk_pll_get_rate()
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)  in rkclk_set_pll()  argument
374 			   pll_con, div->fbdiv, div->refdiv, div->postdiv1,  in rkclk_set_pll()
384 	rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,  in rkclk_set_pll()
388 	rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,  in rkclk_set_pll()
391 	rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,  in rkclk_set_pll()
393 	rk_clrsetreg(&pll_con[1],  in rkclk_set_pll()
401 	while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))  in rkclk_set_pll()
405 	rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,  in rkclk_set_pll()
413 	u32 *pll_con;  in rk3399_pll_get_rate()  local
417 		pll_con = &cru->apll_l_con[0];  in rk3399_pll_get_rate()
420 		pll_con = &cru->apll_b_con[0];  in rk3399_pll_get_rate()
423 		pll_con = &cru->dpll_con[0];  in rk3399_pll_get_rate()
426 		pll_con = &cru->cpll_con[0];  in rk3399_pll_get_rate()
429 		pll_con = &cru->gpll_con[0];  in rk3399_pll_get_rate()
432 		pll_con = &cru->npll_con[0];  in rk3399_pll_get_rate()
435 		pll_con = &cru->vpll_con[0];  in rk3399_pll_get_rate()
438 		pll_con = &cru->vpll_con[0];  in rk3399_pll_get_rate()
442 	return rkclk_pll_get_rate(pll_con);  in rk3399_pll_get_rate()
517 	u32 *pll_con;  in rk3399_configure_cpu()  local
523 		pll_con = &cru->apll_l_con[0];  in rk3399_configure_cpu()
529 		pll_con = &cru->apll_b_con[0];  in rk3399_configure_cpu()
534 	rkclk_set_pll(pll_con, apll_cfgs[freq]);  in rk3399_configure_cpu()