Lines Matching full:cru
21 #include <dt-bindings/clock/rk3368-cru.h>
223 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() argument
228 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
249 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
252 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
293 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) in rk3368_mmc_get_clk() argument
312 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
388 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_clk() local
409 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
413 return rk3368_mmc_get_clk(cru, clk_id); in rk3368_mmc_set_clk()
418 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_ddr_set_clk() argument
441 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
448 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_gmac_set_clk() argument
456 if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) { in rk3368_gmac_set_clk()
460 u32 con = readl(&cru->clksel_con[43]); in rk3368_gmac_set_clk()
476 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK, in rk3368_gmac_set_clk()
495 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
514 static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id) in rk3368_spi_get_clk() argument
529 val = readl(&cru->clksel_con[spiclk->reg]); in rk3368_spi_get_clk()
536 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk() argument
554 rk_clrsetreg(&cru->clksel_con[spiclk->reg], in rk3368_spi_set_clk()
560 return rk3368_spi_get_clk(cru, clk_id); in rk3368_spi_set_clk()
563 static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru) in rk3368_saradc_get_clk() argument
567 val = readl(&cru->clksel_con[25]); in rk3368_saradc_get_clk()
574 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk() argument
581 rk_clrsetreg(&cru->clksel_con[25], in rk3368_saradc_set_clk()
585 return rk3368_saradc_get_clk(cru); in rk3368_saradc_set_clk()
588 static ulong rk3368_bus_get_clk(struct rk3368_cru *cru, ulong clk_id) in rk3368_bus_get_clk() argument
594 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
596 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_bus_get_clk()
599 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
601 parent = rk3368_bus_get_clk(cru, ACLK_BUS); in rk3368_bus_get_clk()
608 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
610 parent = rk3368_bus_get_clk(cru, ACLK_BUS); in rk3368_bus_get_clk()
619 static ulong rk3368_bus_set_clk(struct rk3368_cru *cru, in rk3368_bus_set_clk() argument
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
632 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
638 src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru, in rk3368_bus_set_clk()
642 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
647 src_clk_div = DIV_ROUND_UP(rk3368_bus_get_clk(cru, in rk3368_bus_set_clk()
651 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
659 return rk3368_bus_get_clk(cru, clk_id); in rk3368_bus_set_clk()
662 static ulong rk3368_peri_get_clk(struct rk3368_cru *cru, ulong clk_id) in rk3368_peri_get_clk() argument
668 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
670 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_peri_get_clk()
673 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
675 parent = rk3368_peri_get_clk(cru, ACLK_PERI); in rk3368_peri_get_clk()
682 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
684 parent = rk3368_peri_get_clk(cru, ACLK_PERI); in rk3368_peri_get_clk()
693 static ulong rk3368_peri_set_clk(struct rk3368_cru *cru, in rk3368_peri_set_clk() argument
704 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_peri_set_clk()
706 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
712 src_clk_div = DIV_ROUND_UP(rk3368_peri_get_clk(cru, in rk3368_peri_set_clk()
716 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
721 src_clk_div = DIV_ROUND_UP(rk3368_peri_get_clk(cru, in rk3368_peri_set_clk()
725 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
734 return rk3368_peri_get_clk(cru, clk_id); in rk3368_peri_set_clk()
738 static ulong rk3368_vop_get_clk(struct rk3368_cru *cru, int clk_id) in rk3368_vop_get_clk() argument
744 con = readl(&cru->clksel_con[20]); in rk3368_vop_get_clk()
746 parent = rkclk_pll_get_rate(cru, NPLL); in rk3368_vop_get_clk()
749 con = readl(&cru->clksel_con[19]); in rk3368_vop_get_clk()
755 parent = rkclk_pll_get_rate(cru, CPLL); in rk3368_vop_get_clk()
757 parent = rkclk_pll_get_rate(cru, GPLL); in rk3368_vop_get_clk()
768 static ulong rk3368_vop_set_clk(struct rk3368_cru *cru, int clk_id, uint hz) in rk3368_vop_set_clk() argument
777 rkclk_set_pll(cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_vop_set_clk()
784 rkclk_set_pll(cru, NPLL, &npll_config); in rk3368_vop_set_clk()
787 rk_clrsetreg(&cru->clksel_con[20], in rk3368_vop_set_clk()
794 if ((rkclk_pll_get_rate(cru, CPLL) % hz) == 0) { in rk3368_vop_set_clk()
795 lcdc_div = rkclk_pll_get_rate(cru, CPLL) / hz; in rk3368_vop_set_clk()
796 rk_clrsetreg(&cru->clksel_con[19], in rk3368_vop_set_clk()
806 lcdc_div = rkclk_pll_get_rate(cru, GPLL) / hz; in rk3368_vop_set_clk()
807 rk_clrsetreg(&cru->clksel_con[19], in rk3368_vop_set_clk()
827 struct rk3368_cru *cru = priv->cru; in rk3368_alive_get_clk() local
830 con = readl(&cru->clksel_con[10]); in rk3368_alive_get_clk()
839 struct rk3368_cru *cru = priv->cru; in rk3368_crypto_get_rate() local
842 val = readl(&cru->clksel_con[10]); in rk3368_crypto_get_rate()
845 return DIV_TO_RATE(rk3368_bus_get_clk(priv->cru, ACLK_BUS), div); in rk3368_crypto_get_rate()
851 struct rk3368_cru *cru = priv->cru; in rk3368_crypto_set_rate() local
855 p_rate = rk3368_bus_get_clk(priv->cru, ACLK_BUS); in rk3368_crypto_set_rate()
859 rk_clrsetreg(&cru->clksel_con[10], in rk3368_crypto_set_rate()
870 struct rk3368_cru *cru = priv->cru; in rk3368_armclk_set_clk() local
894 old_rate = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_armclk_set_clk()
898 old_rate = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_armclk_set_clk()
904 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
905 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_armclk_set_clk()
909 rk_clrsetreg(&cru->clksel_con[con_id + 1], in rk3368_armclk_set_clk()
914 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_armclk_set_clk()
918 rk_clrsetreg(&cru->clksel_con[con_id + 1], in rk3368_armclk_set_clk()
922 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
925 return rkclk_pll_get_rate(priv->cru, pll_id); in rk3368_armclk_set_clk()
941 rate = rkclk_pll_get_rate(priv->cru, clk->id - 1); in rk3368_clk_get_rate()
944 rate = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_get_rate()
947 rate = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_get_rate()
950 rate = rk3368_spi_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
959 rate = rk3368_bus_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
968 rate = rk3368_peri_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
973 rate = rk3368_mmc_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
977 rate = rk3368_saradc_get_clk(priv->cru); in rk3368_clk_get_rate()
982 rate = rk3368_vop_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
1014 ret = rkclk_set_pll(priv->cru, clk->id - 1, &pll_config); in rk3368_clk_set_rate()
1027 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1031 ret = rk3368_ddr_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1037 rate = rk3368_bus_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1042 rate = rk3368_peri_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1053 ret = rk3368_gmac_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1057 ret = rk3368_saradc_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1062 ret = rk3368_vop_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1081 struct rk3368_cru *cru = priv->cru; in rk3368_gmac_set_parent() local
1092 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
1108 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
1141 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_get_phase() local
1152 raw_value = readl(&cru->emmc_con[1]); in rk3368_mmc_get_phase()
1154 raw_value = readl(&cru->sdmmc_con[1]); in rk3368_mmc_get_phase()
1156 raw_value = readl(&cru->sdio0_con[1]); in rk3368_mmc_get_phase()
1177 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_phase() local
1207 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rk3368_mmc_set_phase()
1209 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk3368_mmc_set_phase()
1211 writel(raw_value | 0xffff0000, &cru->sdio0_con[1]); in rk3368_mmc_set_phase()
1266 static void rkclk_init(struct rk3368_cru *cru) in rkclk_init() argument
1270 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg); in rkclk_init()
1271 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg); in rkclk_init()
1277 rkclk_set_pll(cru, GPLL, &gpll_init_cfg); in rkclk_init()
1278 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
1280 rk_clrsetreg(&cru->clksel_con[37], (1 << 8), 1 << 8); in rkclk_init()
1281 apllb = rkclk_pll_get_rate(cru, APLLB); in rkclk_init()
1282 aplll = rkclk_pll_get_rate(cru, APLLL); in rkclk_init()
1283 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
1284 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
1285 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
1299 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3368_clk_probe()
1303 priv->armlclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_probe()
1305 priv->armbclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_probe()
1307 rkclk_init(priv->cru); in rk3368_clk_probe()
1309 rkclk_set_pll(priv->cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_clk_probe()
1311 priv->armlclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_probe()
1313 priv->armbclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_probe()
1328 priv->cru = dev_read_addr_ptr(dev); in rk3368_clk_ofdata_to_platdata()
1371 { .compatible = "rockchip,rk3368-cru" },
1410 printf("%s failed to get cru device\n", __func__); in soc_clk_dump()