Lines Matching +full:clk +full:- +full:div
3 * Author: Andy Yan <andy.yan@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
21 #include <dt-bindings/clock/rk3368-cru.h>
62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
121 static ulong rk3368_clk_get_rate(struct clk *clk);
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config() argument
154 return -EINVAL; in pll_para_config()
165 div->nr = best_div->nr; in pll_para_config()
166 div->nf = best_div->nf; in pll_para_config()
167 div->no = best_div->no; in pll_para_config()
168 div->nb = best_div->nb; in pll_para_config()
183 return -1; in pll_para_config()
186 div->no = no; in pll_para_config()
199 diff_khz = vco_khz - nf * fref_khz; in pll_para_config()
202 diff_khz = fref_khz - diff_khz; in pll_para_config()
209 div->nr = nr; in pll_para_config()
210 div->nf = nf; in pll_para_config()
216 return -EINVAL; in pll_para_config()
228 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
230 con = readl(&pll->con3); in rkclk_pll_get_rate()
236 con = readl(&pll->con0); in rkclk_pll_get_rate()
239 con = readl(&pll->con1); in rkclk_pll_get_rate()
250 const struct pll_div *div) in rkclk_set_pll() argument
252 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
254 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
255 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
258 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
261 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
264 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, in rkclk_set_pll()
265 ((div->nr - 1) << PLL_NR_SHIFT) | in rkclk_set_pll()
266 ((div->no - 1) << PLL_OD_SHIFT)); in rkclk_set_pll()
267 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
272 if (div->nb) in rkclk_set_pll()
273 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, div->nb - 1); in rkclk_set_pll()
275 clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
280 rk_clrreg(&pll->con3, PLL_RESET_MASK); in rkclk_set_pll()
283 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
286 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
295 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
309 return -EINVAL; in rk3368_mmc_get_clk()
312 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
325 return -EINVAL; in rk3368_mmc_get_clk()
327 div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT; in rk3368_mmc_get_clk()
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
330 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate); in rk3368_mmc_get_clk()
334 static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk, in rk3368_mmc_find_best_rate_and_parent() argument
354 * Find the largest rate no larger than the target-rate for in rk3368_mmc_find_best_rate_and_parent()
358 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent() local
359 u32 adj_div = div; in rk3368_mmc_find_best_rate_and_parent()
362 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n", in rk3368_mmc_find_best_rate_and_parent()
363 __func__, rate, parents[i].mux, parents[i].rate, div); in rk3368_mmc_find_best_rate_and_parent()
366 if ((div - 1) > MMC_CLK_DIV_MASK) in rk3368_mmc_find_best_rate_and_parent()
376 *best_div = div - 1; in rk3368_mmc_find_best_rate_and_parent()
385 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate) in rk3368_mmc_set_clk() argument
387 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_mmc_set_clk()
388 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_clk()
389 ulong clk_id = clk->id; in rk3368_mmc_set_clk()
390 u32 con_id, mux = 0, div = 0; in rk3368_mmc_set_clk() local
393 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div); in rk3368_mmc_set_clk()
406 return -EINVAL; in rk3368_mmc_set_clk()
409 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
411 mux | div); in rk3368_mmc_set_clk()
456 if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) { in rk3368_gmac_set_clk()
460 u32 con = readl(&cru->clksel_con[43]); in rk3368_gmac_set_clk()
462 u8 div; in rk3368_gmac_set_clk() local
472 return -EPERM; in rk3368_gmac_set_clk()
474 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
475 if (div <= 0x1f) in rk3368_gmac_set_clk()
476 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK, in rk3368_gmac_set_clk()
477 div << GMAC_DIV_CON_SHIFT); in rk3368_gmac_set_clk()
479 debug("Unsupported div for gmac:%d\n", div); in rk3368_gmac_set_clk()
481 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
489 * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
490 * to select either CPLL or GPLL as the clock-parent. The location within
511 return (val >> shift) & ((1 << width) - 1); in extract_bits()
517 u32 div, val; in rk3368_spi_get_clk() local
521 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_get_clk()
525 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3368_spi_get_clk()
526 return -EINVAL; in rk3368_spi_get_clk()
529 val = readl(&cru->clksel_con[spiclk->reg]); in rk3368_spi_get_clk()
530 div = extract_bits(val, 7, spiclk->div_shift); in rk3368_spi_get_clk()
532 debug("%s: div 0x%x\n", __func__, div); in rk3368_spi_get_clk()
533 return DIV_TO_RATE(GPLL_HZ, div); in rk3368_spi_get_clk()
546 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_set_clk()
550 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3368_spi_set_clk()
551 return -EINVAL; in rk3368_spi_set_clk()
554 rk_clrsetreg(&cru->clksel_con[spiclk->reg], in rk3368_spi_set_clk()
555 ((0x7f << spiclk->div_shift) | in rk3368_spi_set_clk()
556 (0x1 << spiclk->sel_shift)), in rk3368_spi_set_clk()
557 ((src_clk_div << spiclk->div_shift) | in rk3368_spi_set_clk()
558 (1 << spiclk->sel_shift))); in rk3368_spi_set_clk()
565 u32 div, val; in rk3368_saradc_get_clk() local
567 val = readl(&cru->clksel_con[25]); in rk3368_saradc_get_clk()
568 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, in rk3368_saradc_get_clk()
571 return DIV_TO_RATE(OSC_HZ, div); in rk3368_saradc_get_clk()
578 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
581 rk_clrsetreg(&cru->clksel_con[25], in rk3368_saradc_set_clk()
590 u32 div, con, parent; in rk3368_bus_get_clk() local
594 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
595 div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT; in rk3368_bus_get_clk()
599 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
600 div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT; in rk3368_bus_get_clk()
608 con = readl(&cru->clksel_con[8]); in rk3368_bus_get_clk()
609 div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT; in rk3368_bus_get_clk()
613 return -ENOENT; in rk3368_bus_get_clk()
616 return DIV_TO_RATE(parent, div); in rk3368_bus_get_clk()
631 assert(src_clk_div - 1 < 31); in rk3368_bus_set_clk()
632 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
635 (src_clk_div - 1) << ACLK_BUS_DIV_CON_SHIFT); in rk3368_bus_set_clk()
641 assert(src_clk_div - 1 < 3); in rk3368_bus_set_clk()
642 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
644 (src_clk_div - 1) << HCLK_BUS_DIV_CON_SHIFT); in rk3368_bus_set_clk()
650 assert(src_clk_div - 1 < 3); in rk3368_bus_set_clk()
651 rk_clrsetreg(&cru->clksel_con[8], in rk3368_bus_set_clk()
653 (src_clk_div - 1) << PCLK_BUS_DIV_CON_SHIFT); in rk3368_bus_set_clk()
657 return -EINVAL; in rk3368_bus_set_clk()
664 u32 div, con, parent; in rk3368_peri_get_clk() local
668 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
669 div = (con & ACLK_PERI_DIV_CON_MASK) >> ACLK_PERI_DIV_CON_SHIFT; in rk3368_peri_get_clk()
673 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
674 div = (con & HCLK_PERI_DIV_CON_MASK) >> HCLK_PERI_DIV_CON_SHIFT; in rk3368_peri_get_clk()
682 con = readl(&cru->clksel_con[9]); in rk3368_peri_get_clk()
683 div = (con & PCLK_PERI_DIV_CON_MASK) >> PCLK_PERI_DIV_CON_SHIFT; in rk3368_peri_get_clk()
687 return -ENOENT; in rk3368_peri_get_clk()
690 return DIV_TO_RATE(parent, div); in rk3368_peri_get_clk()
705 assert(src_clk_div - 1 < 31); in rk3368_peri_set_clk()
706 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
709 (src_clk_div - 1) << ACLK_PERI_DIV_CON_SHIFT); in rk3368_peri_set_clk()
715 assert(src_clk_div - 1 < 3); in rk3368_peri_set_clk()
716 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
718 (src_clk_div - 1) << HCLK_PERI_DIV_CON_SHIFT); in rk3368_peri_set_clk()
724 assert(src_clk_div - 1 < 3); in rk3368_peri_set_clk()
725 rk_clrsetreg(&cru->clksel_con[9], in rk3368_peri_set_clk()
727 (src_clk_div - 1) << PCLK_PERI_DIV_CON_SHIFT); in rk3368_peri_set_clk()
731 return -EINVAL; in rk3368_peri_set_clk()
740 u32 div, con, parent, sel; in rk3368_vop_get_clk() local
744 con = readl(&cru->clksel_con[20]); in rk3368_vop_get_clk()
745 div = con & DCLK_VOP_DIV_MASK; in rk3368_vop_get_clk()
749 con = readl(&cru->clksel_con[19]); in rk3368_vop_get_clk()
750 div = con & ACLK_VOP_DIV_MASK; in rk3368_vop_get_clk()
762 return -EINVAL; in rk3368_vop_get_clk()
765 return DIV_TO_RATE(parent, div); in rk3368_vop_get_clk()
786 /* vop dclk source clk: npll,dclk_div: 1 */ in rk3368_vop_set_clk()
787 rk_clrsetreg(&cru->clksel_con[20], in rk3368_vop_set_clk()
791 (lcdc_div - 1) << DCLK_VOP_DIV_SHIFT); in rk3368_vop_set_clk()
796 rk_clrsetreg(&cru->clksel_con[19], in rk3368_vop_set_clk()
803 (lcdc_div - 1) << in rk3368_vop_set_clk()
807 rk_clrsetreg(&cru->clksel_con[19], in rk3368_vop_set_clk()
814 (lcdc_div - 1) << in rk3368_vop_set_clk()
819 return -EINVAL; in rk3368_vop_set_clk()
827 struct rk3368_cru *cru = priv->cru; in rk3368_alive_get_clk()
828 u32 div, con, parent; in rk3368_alive_get_clk() local
830 con = readl(&cru->clksel_con[10]); in rk3368_alive_get_clk()
831 div = (con & PCLK_ALIVE_DIV_CON_MASK) >> in rk3368_alive_get_clk()
834 return DIV_TO_RATE(parent, div); in rk3368_alive_get_clk()
839 struct rk3368_cru *cru = priv->cru; in rk3368_crypto_get_rate()
840 u32 div, val; in rk3368_crypto_get_rate() local
842 val = readl(&cru->clksel_con[10]); in rk3368_crypto_get_rate()
843 div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT; in rk3368_crypto_get_rate()
845 return DIV_TO_RATE(rk3368_bus_get_clk(priv->cru, ACLK_BUS), div); in rk3368_crypto_get_rate()
851 struct rk3368_cru *cru = priv->cru; in rk3368_crypto_set_rate()
855 p_rate = rk3368_bus_get_clk(priv->cru, ACLK_BUS); in rk3368_crypto_set_rate()
856 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; in rk3368_crypto_set_rate()
859 rk_clrsetreg(&cru->clksel_con[10], in rk3368_crypto_set_rate()
870 struct rk3368_cru *cru = priv->cru; in rk3368_armclk_set_clk()
880 return -EINVAL; in rk3368_armclk_set_clk()
894 old_rate = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_armclk_set_clk()
898 old_rate = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_armclk_set_clk()
904 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
905 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_armclk_set_clk()
909 rk_clrsetreg(&cru->clksel_con[con_id + 1], in rk3368_armclk_set_clk()
911 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3368_armclk_set_clk()
912 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3368_armclk_set_clk()
914 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_armclk_set_clk()
918 rk_clrsetreg(&cru->clksel_con[con_id + 1], in rk3368_armclk_set_clk()
920 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3368_armclk_set_clk()
921 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3368_armclk_set_clk()
922 ret = rkclk_set_pll(priv->cru, pll_id, &pll_config); in rk3368_armclk_set_clk()
925 return rkclk_pll_get_rate(priv->cru, pll_id); in rk3368_armclk_set_clk()
928 static ulong rk3368_clk_get_rate(struct clk *clk) in rk3368_clk_get_rate() argument
930 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_clk_get_rate()
933 debug("%s: id %ld\n", __func__, clk->id); in rk3368_clk_get_rate()
934 switch (clk->id) { in rk3368_clk_get_rate()
941 rate = rkclk_pll_get_rate(priv->cru, clk->id - 1); in rk3368_clk_get_rate()
944 rate = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_get_rate()
947 rate = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_get_rate()
950 rate = rk3368_spi_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
959 rate = rk3368_bus_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
968 rate = rk3368_peri_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
973 rate = rk3368_mmc_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
977 rate = rk3368_saradc_get_clk(priv->cru); in rk3368_clk_get_rate()
982 rate = rk3368_vop_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
992 return -ENOENT; in rk3368_clk_get_rate()
997 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) in rk3368_clk_set_rate() argument
999 __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_clk_set_rate()
1004 switch (clk->id) { in rk3368_clk_set_rate()
1014 ret = rkclk_set_pll(priv->cru, clk->id - 1, &pll_config); in rk3368_clk_set_rate()
1017 if (priv->armbclk_hz) in rk3368_clk_set_rate()
1018 ret = rk3368_armclk_set_clk(priv, clk->id, rate); in rk3368_clk_set_rate()
1019 priv->armbclk_hz = rate; in rk3368_clk_set_rate()
1022 if (priv->armlclk_hz) in rk3368_clk_set_rate()
1023 ret = rk3368_armclk_set_clk(priv, clk->id, rate); in rk3368_clk_set_rate()
1024 priv->armlclk_hz = rate; in rk3368_clk_set_rate()
1027 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1031 ret = rk3368_ddr_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1037 rate = rk3368_bus_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1042 rate = rk3368_peri_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1047 ret = rk3368_mmc_set_clk(clk, rate); in rk3368_clk_set_rate()
1053 ret = rk3368_gmac_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1057 ret = rk3368_saradc_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1062 ret = rk3368_vop_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1072 return -ENOENT; in rk3368_clk_set_rate()
1078 static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent) in rk3368_gmac_set_parent() argument
1080 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_gmac_set_parent()
1081 struct rk3368_cru *cru = priv->cru; in rk3368_gmac_set_parent()
1086 * If the requested parent is in the same clock-controller and in rk3368_gmac_set_parent()
1090 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { in rk3368_gmac_set_parent()
1092 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
1097 * Otherwise, we need to check the clock-output-names of the in rk3368_gmac_set_parent()
1100 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3368_gmac_set_parent()
1101 parent->id, &clock_output_name); in rk3368_gmac_set_parent()
1103 return -ENODATA; in rk3368_gmac_set_parent()
1108 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
1112 return -EINVAL; in rk3368_gmac_set_parent()
1115 static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent) in rk3368_clk_set_parent() argument
1117 switch (clk->id) { in rk3368_clk_set_parent()
1119 return rk3368_gmac_set_parent(clk, parent); in rk3368_clk_set_parent()
1122 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3368_clk_set_parent()
1123 return -ENOENT; in rk3368_clk_set_parent()
1133 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1138 int rk3368_mmc_get_phase(struct clk *clk) in rk3368_mmc_get_phase() argument
1140 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_mmc_get_phase()
1141 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_get_phase()
1146 rate = rk3368_clk_get_rate(clk); in rk3368_mmc_get_phase()
1151 if (clk->id == SCLK_EMMC_SAMPLE) in rk3368_mmc_get_phase()
1152 raw_value = readl(&cru->emmc_con[1]); in rk3368_mmc_get_phase()
1153 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk3368_mmc_get_phase()
1154 raw_value = readl(&cru->sdmmc_con[1]); in rk3368_mmc_get_phase()
1156 raw_value = readl(&cru->sdio0_con[1]); in rk3368_mmc_get_phase()
1174 int rk3368_mmc_set_phase(struct clk *clk, u32 degrees) in rk3368_mmc_set_phase() argument
1176 struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); in rk3368_mmc_set_phase()
1177 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_phase()
1182 rate = rk3368_clk_get_rate(clk); in rk3368_mmc_set_phase()
1192 * don't overflow 32-bit / 64-bit numbers. in rk3368_mmc_set_phase()
1206 if (clk->id == SCLK_EMMC_SAMPLE) in rk3368_mmc_set_phase()
1207 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rk3368_mmc_set_phase()
1208 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk3368_mmc_set_phase()
1209 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk3368_mmc_set_phase()
1211 writel(raw_value | 0xffff0000, &cru->sdio0_con[1]); in rk3368_mmc_set_phase()
1214 degrees, delay_num, raw_value, rk3368_mmc_get_phase(clk)); in rk3368_mmc_set_phase()
1219 static int rk3368_clk_get_phase(struct clk *clk) in rk3368_clk_get_phase() argument
1223 debug("%s %ld\n", __func__, clk->id); in rk3368_clk_get_phase()
1224 switch (clk->id) { in rk3368_clk_get_phase()
1228 ret = rk3368_mmc_get_phase(clk); in rk3368_clk_get_phase()
1231 return -ENOENT; in rk3368_clk_get_phase()
1237 static int rk3368_clk_set_phase(struct clk *clk, int degrees) in rk3368_clk_set_phase() argument
1241 debug("%s %ld\n", __func__, clk->id); in rk3368_clk_set_phase()
1242 switch (clk->id) { in rk3368_clk_set_phase()
1246 ret = rk3368_mmc_set_phase(clk, degrees); in rk3368_clk_set_phase()
1249 return -ENOENT; in rk3368_clk_set_phase()
1280 rk_clrsetreg(&cru->clksel_con[37], (1 << 8), 1 << 8); in rkclk_init()
1299 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3368_clk_probe()
1301 priv->sync_kernel = false; in rk3368_clk_probe()
1302 if (!priv->armlclk_enter_hz) in rk3368_clk_probe()
1303 priv->armlclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_probe()
1304 if (!priv->armbclk_enter_hz) in rk3368_clk_probe()
1305 priv->armbclk_enter_hz = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_probe()
1307 rkclk_init(priv->cru); in rk3368_clk_probe()
1309 rkclk_set_pll(priv->cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_clk_probe()
1310 if (!priv->armlclk_init_hz) in rk3368_clk_probe()
1311 priv->armlclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_probe()
1312 if (!priv->armbclk_init_hz) in rk3368_clk_probe()
1313 priv->armbclk_init_hz = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_probe()
1314 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk3368_clk_probe()
1319 priv->sync_kernel = true; in rk3368_clk_probe()
1328 priv->cru = dev_read_addr_ptr(dev); in rk3368_clk_ofdata_to_platdata()
1348 priv->glb_srst_fst_value = offsetof(struct rk3368_cru, in rk3368_clk_bind()
1350 priv->glb_srst_snd_value = offsetof(struct rk3368_cru, in rk3368_clk_bind()
1352 sys_child->priv = priv; in rk3368_clk_bind()
1361 sf_priv->sf_reset_offset = offsetof(struct rk3368_cru, in rk3368_clk_bind()
1363 sf_priv->sf_reset_num = 15; in rk3368_clk_bind()
1364 sf_child->priv = sf_priv; in rk3368_clk_bind()
1371 { .compatible = "rockchip,rk3368-cru" },
1391 * soc_clk_dump() - Print clock frequencies
1394 * Implementation for the clk dump command.
1401 struct clk clk; in soc_clk_dump() local
1415 printf("CLK: (%s. arml: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1416 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1417 priv->armlclk_enter_hz / 1000, in soc_clk_dump()
1418 priv->armlclk_init_hz / 1000, in soc_clk_dump()
1419 priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0, in soc_clk_dump()
1420 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1421 printf("CLK: (%s. armb: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1422 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1423 priv->armbclk_enter_hz / 1000, in soc_clk_dump()
1424 priv->armbclk_init_hz / 1000, in soc_clk_dump()
1425 priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0, in soc_clk_dump()
1426 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1429 if (clk_dump->name) { in soc_clk_dump()
1430 clk.id = clk_dump->id; in soc_clk_dump()
1431 if (clk_dump->is_cru) in soc_clk_dump()
1432 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1436 rate = clk_get_rate(&clk); in soc_clk_dump()
1437 clk_free(&clk); in soc_clk_dump()
1440 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1443 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1447 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1450 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()