62 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()
250 			 const struct pll_div *div)  in rkclk_set_pll()
295 	u32 div, con, con_id, rate;  in rk3368_mmc_get_clk()  local
358 		u32 div = DIV_ROUND_UP(parent_rate, rate);  in rk3368_mmc_find_best_rate_and_parent()  local
390 	u32 con_id, mux = 0, div = 0;  in rk3368_mmc_set_clk()  local
462 		u8 div;  in rk3368_gmac_set_clk()  local
517 	u32 div, val;  in rk3368_spi_get_clk()  local
565 	u32 div, val;  in rk3368_saradc_get_clk()  local
590 	u32 div, con, parent;  in rk3368_bus_get_clk()  local
664 	u32 div, con, parent;  in rk3368_peri_get_clk()  local
740 	u32 div, con, parent, sel;  in rk3368_vop_get_clk()  local
828 	u32 div, con, parent;  in rk3368_alive_get_clk()  local
840 	u32 div, val;  in rk3368_crypto_get_rate()  local