194 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_i2c_get_clk()
203 	src_clk_div = priv->gpll_hz / hz;  in rk3328_i2c_set_clk()
240 	return DIV_TO_RATE(priv->gpll_hz, src_clk_div);  in rk3328_i2c_set_clk()
265 			pll_rate = priv->gpll_hz;  in rk3328_gmac2io_set_clk()
341 		return DIV_TO_RATE(priv->gpll_hz, div) / 2;  in rk3328_mmc_get_clk()
365 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate);  in rk3328_mmc_set_clk()
393 		p_rate = priv->gpll_hz;  in rk3328_spi_get_clk()
403 	u32 div = priv->gpll_hz / hz;  in rk3328_spi_set_clk()
410 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_spi_set_clk()
422 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_pwm_get_clk()
428 	u32 div = priv->gpll_hz / hz;  in rk3328_pwm_set_clk()
435 	return DIV_TO_RATE(priv->gpll_hz, div);  in rk3328_pwm_set_clk()
567 				src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3328_vop_set_clk()
743 		parent = priv->gpll_hz;  in rk3328_crypto_get_clk()
758 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3328_crypto_set_clk()
787 	if (!priv->gpll_hz) {  in rk3328_clk_get_rate()
788 		priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL],  in rk3328_clk_get_rate()
790 		debug("%s gpll=%lu\n", __func__, priv->gpll_hz);  in rk3328_clk_get_rate()
887 		priv->gpll_hz = rate;  in rk3328_clk_set_rate()
1286 	priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL],  in rkclk_init()
1302 	priv->gpll_hz = GPLL_HZ;  in rkclk_init()