Lines Matching +full:clk +full:- +full:div
4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/rk3328-cru.h>
24 ((input_rate) / (output_rate) - 1);
25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
120 struct rk3328_cru *cru = priv->cru; in rk3328_armclk_set_clk()
127 return -EINVAL; in rk3328_armclk_set_clk()
136 priv->cru, NPLL); in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
140 return -EINVAL; in rk3328_armclk_set_clk()
141 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
145 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
147 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3328_armclk_set_clk()
148 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3328_armclk_set_clk()
150 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
152 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3328_armclk_set_clk()
153 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3328_armclk_set_clk()
154 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
159 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
160 return -EINVAL; in rk3328_armclk_set_clk()
163 return rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], priv->cru, NPLL); in rk3328_armclk_set_clk()
169 struct rk3328_cru *cru = priv->cru; in rk3328_i2c_get_clk()
170 u32 div, con; in rk3328_i2c_get_clk() local
174 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
175 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
178 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
179 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
182 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
183 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
186 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
187 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
191 return -EINVAL; in rk3328_i2c_get_clk()
194 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_i2c_get_clk()
200 struct rk3328_cru *cru = priv->cru; in rk3328_i2c_set_clk()
203 src_clk_div = priv->gpll_hz / hz; in rk3328_i2c_set_clk()
204 assert(src_clk_div - 1 < 127); in rk3328_i2c_set_clk()
208 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
211 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
215 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
218 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
222 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
225 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
229 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
232 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk3328_i2c_set_clk()
237 return -EINVAL; in rk3328_i2c_set_clk()
240 return DIV_TO_RATE(priv->gpll_hz, src_clk_div); in rk3328_i2c_set_clk()
245 struct rk3328_cru *cru = priv->cru; in rk3328_gmac2io_set_clk()
252 * The RGMII CLK can be derived either from an external "clkin" in rk3328_gmac2io_set_clk()
255 if (readl(&grf->mac_con[1]) & BIT(10) && in rk3328_gmac2io_set_clk()
256 readl(&grf->soc_con[4]) & BIT(14)) { in rk3328_gmac2io_set_clk()
260 u32 con = readl(&cru->clksel_con[27]); in rk3328_gmac2io_set_clk()
262 u8 div; in rk3328_gmac2io_set_clk() local
265 pll_rate = priv->gpll_hz; in rk3328_gmac2io_set_clk()
267 pll_rate = priv->cpll_hz; in rk3328_gmac2io_set_clk()
269 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
270 if (div <= 0x1f) in rk3328_gmac2io_set_clk()
271 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK, in rk3328_gmac2io_set_clk()
272 div << GMAC2IO_CLK_DIV_SHIFT); in rk3328_gmac2io_set_clk()
274 debug("Unsupported div for gmac:%d\n", div); in rk3328_gmac2io_set_clk()
276 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
284 u32 con = readl(&cru->clksel_con[26]); in rk3328_gmac2phy_src_set_clk()
286 u8 div; in rk3328_gmac2phy_src_set_clk() local
293 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2phy_src_set_clk()
294 if (div <= 0x1f) in rk3328_gmac2phy_src_set_clk()
295 rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, in rk3328_gmac2phy_src_set_clk()
296 div << GMAC2PHY_CLK_DIV_SHIFT); in rk3328_gmac2phy_src_set_clk()
298 debug("Unsupported div for gmac:%d\n", div); in rk3328_gmac2phy_src_set_clk()
300 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2phy_src_set_clk()
308 if (readl(&grf->mac_con[2]) & BIT(10)) in rk3328_gmac2phy_set_clk()
318 struct rk3328_cru *cru = priv->cru; in rk3328_mmc_get_clk()
319 u32 div, con, con_id; in rk3328_mmc_get_clk() local
332 return -EINVAL; in rk3328_mmc_get_clk()
334 con = readl(&cru->clksel_con[con_id]); in rk3328_mmc_get_clk()
335 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; in rk3328_mmc_get_clk()
339 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3328_mmc_get_clk()
341 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk3328_mmc_get_clk()
347 struct rk3328_cru *cru = priv->cru; in rk3328_mmc_set_clk()
361 return -EINVAL; in rk3328_mmc_set_clk()
364 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rk3328_mmc_set_clk()
365 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk3328_mmc_set_clk()
370 rk_clrsetreg(&cru->clksel_con[con_id], in rk3328_mmc_set_clk()
373 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); in rk3328_mmc_set_clk()
375 rk_clrsetreg(&cru->clksel_con[con_id], in rk3328_mmc_set_clk()
378 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); in rk3328_mmc_set_clk()
386 struct rk3328_cru *cru = priv->cru; in rk3328_spi_get_clk()
387 u32 div, con, mux, p_rate; in rk3328_spi_get_clk() local
389 con = readl(&cru->clksel_con[24]); in rk3328_spi_get_clk()
390 div = (con & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT; in rk3328_spi_get_clk()
393 p_rate = priv->gpll_hz; in rk3328_spi_get_clk()
395 p_rate = priv->cpll_hz; in rk3328_spi_get_clk()
397 return DIV_TO_RATE(p_rate, div); in rk3328_spi_get_clk()
402 struct rk3328_cru *cru = priv->cru; in rk3328_spi_set_clk()
403 u32 div = priv->gpll_hz / hz; in rk3328_spi_set_clk() local
405 rk_clrsetreg(&cru->clksel_con[24], in rk3328_spi_set_clk()
408 (div - 1) << CLK_SPI_DIV_CON_SHIFT); in rk3328_spi_set_clk()
410 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_spi_set_clk()
416 struct rk3328_cru *cru = priv->cru; in rk3328_pwm_get_clk()
417 u32 div, con; in rk3328_pwm_get_clk() local
419 con = readl(&cru->clksel_con[24]); in rk3328_pwm_get_clk()
420 div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT; in rk3328_pwm_get_clk()
422 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_pwm_get_clk()
427 struct rk3328_cru *cru = priv->cru; in rk3328_pwm_set_clk()
428 u32 div = priv->gpll_hz / hz; in rk3328_pwm_set_clk() local
430 rk_clrsetreg(&cru->clksel_con[24], in rk3328_pwm_set_clk()
433 (div - 1) << CLK_PWM_DIV_CON_SHIFT); in rk3328_pwm_set_clk()
435 return DIV_TO_RATE(priv->gpll_hz, div); in rk3328_pwm_set_clk()
440 struct rk3328_cru *cru = priv->cru; in rk3328_saradc_get_clk()
441 u32 div, val; in rk3328_saradc_get_clk() local
443 val = readl(&cru->clksel_con[23]); in rk3328_saradc_get_clk()
444 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, in rk3328_saradc_get_clk()
447 return DIV_TO_RATE(OSC_HZ, div); in rk3328_saradc_get_clk()
452 struct rk3328_cru *cru = priv->cru; in rk3328_saradc_set_clk()
455 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
458 rk_clrsetreg(&cru->clksel_con[23], in rk3328_saradc_set_clk()
467 struct rk3328_cru *cru = priv->cru; in rk3328_tsadc_get_clk()
468 u32 div, val; in rk3328_tsadc_get_clk() local
470 val = readl(&cru->clksel_con[22]); in rk3328_tsadc_get_clk()
471 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, in rk3328_tsadc_get_clk()
474 return DIV_TO_RATE(OSC_HZ, div); in rk3328_tsadc_get_clk()
479 struct rk3328_cru *cru = priv->cru; in rk3328_tsadc_set_clk()
482 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_tsadc_set_clk()
485 rk_clrsetreg(&cru->clksel_con[22], in rk3328_tsadc_set_clk()
494 struct rk3328_cru *cru = priv->cru; in rk3328_vop_get_clk()
495 u32 div, con, parent; in rk3328_vop_get_clk() local
500 con = readl(&cru->clksel_con[39]); in rk3328_vop_get_clk()
501 div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT; in rk3328_vop_get_clk()
502 parent = priv->cpll_hz; in rk3328_vop_get_clk()
506 con = readl(&cru->clksel_con[37]); in rk3328_vop_get_clk()
507 div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT; in rk3328_vop_get_clk()
508 parent = priv->cpll_hz; in rk3328_vop_get_clk()
513 con = readl(&cru->clksel_con[37]); in rk3328_vop_get_clk()
514 div = (con & HCLK_VIO_DIV_CON_MASK) >> HCLK_VIO_DIV_CON_SHIFT; in rk3328_vop_get_clk()
517 return -ENOENT; in rk3328_vop_get_clk()
520 return DIV_TO_RATE(parent, div); in rk3328_vop_get_clk()
526 struct rk3328_cru *cru = priv->cru; in rk3328_vop_set_clk()
530 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
531 assert(src_clk_div - 1 < 31); in rk3328_vop_set_clk()
536 rk_clrsetreg(&cru->clksel_con[39], in rk3328_vop_set_clk()
539 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); in rk3328_vop_set_clk()
543 rk_clrsetreg(&cru->clksel_con[37], in rk3328_vop_set_clk()
546 (src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT); in rk3328_vop_set_clk()
553 rk_clrsetreg(&cru->clksel_con[37], in rk3328_vop_set_clk()
555 (src_clk_div - 1) << HCLK_VIO_DIV_CON_SHIFT); in rk3328_vop_set_clk()
558 con = readl(&cru->clksel_con[40]); in rk3328_vop_set_clk()
561 parent = readl(&cru->clksel_con[40]); in rk3328_vop_set_clk()
565 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
567 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3328_vop_set_clk()
569 rk_clrsetreg(&cru->clksel_con[40], in rk3328_vop_set_clk()
571 (src_clk_div - 1) << in rk3328_vop_set_clk()
577 return -EINVAL; in rk3328_vop_set_clk()
586 struct rk3328_cru *cru = priv->cru; in rk3328_bus_get_clk()
587 u32 div, con, parent; in rk3328_bus_get_clk() local
591 con = readl(&cru->clksel_con[0]); in rk3328_bus_get_clk()
592 div = (con & ACLK_BUS_DIV_CON_MASK) >> ACLK_BUS_DIV_CON_SHIFT; in rk3328_bus_get_clk()
593 parent = priv->cpll_hz; in rk3328_bus_get_clk()
596 con = readl(&cru->clksel_con[1]); in rk3328_bus_get_clk()
597 div = (con & HCLK_BUS_DIV_CON_MASK) >> HCLK_BUS_DIV_CON_SHIFT; in rk3328_bus_get_clk()
601 con = readl(&cru->clksel_con[1]); in rk3328_bus_get_clk()
602 div = (con & PCLK_BUS_DIV_CON_MASK) >> PCLK_BUS_DIV_CON_SHIFT; in rk3328_bus_get_clk()
606 return -ENOENT; in rk3328_bus_get_clk()
609 return DIV_TO_RATE(parent, div); in rk3328_bus_get_clk()
615 struct rk3328_cru *cru = priv->cru; in rk3328_bus_set_clk()
624 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_bus_set_clk()
625 assert(src_clk_div - 1 < 31); in rk3328_bus_set_clk()
628 rk_clrsetreg(&cru->clksel_con[0], in rk3328_bus_set_clk()
631 (src_clk_div - 1) << ACLK_BUS_DIV_CON_SHIFT); in rk3328_bus_set_clk()
637 assert(src_clk_div - 1 < 3); in rk3328_bus_set_clk()
638 rk_clrsetreg(&cru->clksel_con[1], in rk3328_bus_set_clk()
640 (src_clk_div - 1) << HCLK_BUS_DIV_CON_SHIFT); in rk3328_bus_set_clk()
646 assert(src_clk_div - 1 < 7); in rk3328_bus_set_clk()
647 rk_clrsetreg(&cru->clksel_con[1], in rk3328_bus_set_clk()
649 (src_clk_div - 1) << PCLK_BUS_DIV_CON_SHIFT); in rk3328_bus_set_clk()
653 return -EINVAL; in rk3328_bus_set_clk()
660 struct rk3328_cru *cru = priv->cru; in rk3328_peri_get_clk()
661 u32 div, con, parent; in rk3328_peri_get_clk() local
665 con = readl(&cru->clksel_con[28]); in rk3328_peri_get_clk()
666 div = (con & ACLK_PERI_DIV_CON_MASK) >> ACLK_PERI_DIV_CON_SHIFT; in rk3328_peri_get_clk()
667 parent = priv->cpll_hz; in rk3328_peri_get_clk()
670 con = readl(&cru->clksel_con[29]); in rk3328_peri_get_clk()
671 div = (con & HCLK_PERI_DIV_CON_MASK) >> HCLK_PERI_DIV_CON_SHIFT; in rk3328_peri_get_clk()
675 con = readl(&cru->clksel_con[29]); in rk3328_peri_get_clk()
676 div = (con & PCLK_PERI_DIV_CON_MASK) >> PCLK_PERI_DIV_CON_SHIFT; in rk3328_peri_get_clk()
680 return -ENOENT; in rk3328_peri_get_clk()
683 return DIV_TO_RATE(parent, div); in rk3328_peri_get_clk()
689 struct rk3328_cru *cru = priv->cru; in rk3328_peri_set_clk()
698 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_peri_set_clk()
699 assert(src_clk_div - 1 < 31); in rk3328_peri_set_clk()
702 rk_clrsetreg(&cru->clksel_con[28], in rk3328_peri_set_clk()
705 (src_clk_div - 1) << ACLK_PERI_DIV_CON_SHIFT); in rk3328_peri_set_clk()
711 assert(src_clk_div - 1 < 3); in rk3328_peri_set_clk()
712 rk_clrsetreg(&cru->clksel_con[29], in rk3328_peri_set_clk()
714 (src_clk_div - 1) << HCLK_PERI_DIV_CON_SHIFT); in rk3328_peri_set_clk()
720 assert(src_clk_div - 1 < 7); in rk3328_peri_set_clk()
721 rk_clrsetreg(&cru->clksel_con[29], in rk3328_peri_set_clk()
723 (src_clk_div - 1) << PCLK_PERI_DIV_CON_SHIFT); in rk3328_peri_set_clk()
727 return -EINVAL; in rk3328_peri_set_clk()
736 struct rk3328_cru *cru = priv->cru; in rk3328_crypto_get_clk()
737 u32 div, con, parent; in rk3328_crypto_get_clk() local
741 con = readl(&cru->clksel_con[20]); in rk3328_crypto_get_clk()
742 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in rk3328_crypto_get_clk()
743 parent = priv->gpll_hz; in rk3328_crypto_get_clk()
746 return -ENOENT; in rk3328_crypto_get_clk()
749 return DIV_TO_RATE(parent, div); in rk3328_crypto_get_clk()
755 struct rk3328_cru *cru = priv->cru; in rk3328_crypto_set_clk()
758 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3328_crypto_set_clk()
759 assert(src_clk_div - 1 <= 127); in rk3328_crypto_set_clk()
767 rk_clrsetreg(&cru->clksel_con[20], in rk3328_crypto_set_clk()
770 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk3328_crypto_set_clk()
774 return -EINVAL; in rk3328_crypto_set_clk()
781 static ulong rk3328_clk_get_rate(struct clk *clk) in rk3328_clk_get_rate() argument
783 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); in rk3328_clk_get_rate()
787 if (!priv->gpll_hz) { in rk3328_clk_get_rate()
788 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rk3328_clk_get_rate()
789 priv->cru, GPLL); in rk3328_clk_get_rate()
790 debug("%s gpll=%lu\n", __func__, priv->gpll_hz); in rk3328_clk_get_rate()
792 if (!priv->cpll_hz) { in rk3328_clk_get_rate()
793 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_get_rate()
794 priv->cru, CPLL); in rk3328_clk_get_rate()
795 debug("%s cpll=%lu\n", __func__, priv->cpll_hz); in rk3328_clk_get_rate()
799 switch (clk->id) { in rk3328_clk_get_rate()
805 rate = rockchip_pll_get_rate(&rk3328_pll_clks[clk->id - 1], in rk3328_clk_get_rate()
806 priv->cru, clk->id - 1); in rk3328_clk_get_rate()
810 priv->cru, NPLL); in rk3328_clk_get_rate()
815 rate = rk3328_bus_get_clk(priv, clk->id); in rk3328_clk_get_rate()
820 rate = rk3328_peri_get_clk(priv, clk->id); in rk3328_clk_get_rate()
827 rate = rk3328_mmc_get_clk(priv, clk->id); in rk3328_clk_get_rate()
837 rate = rk3328_i2c_get_clk(priv, clk->id); in rk3328_clk_get_rate()
854 rate = rk3328_vop_get_clk(priv, clk->id); in rk3328_clk_get_rate()
857 rate = rk3328_crypto_get_clk(priv, clk->id); in rk3328_clk_get_rate()
861 return -ENOENT; in rk3328_clk_get_rate()
867 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) in rk3328_clk_set_rate() argument
869 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); in rk3328_clk_set_rate()
872 switch (clk->id) { in rk3328_clk_set_rate()
876 ret = rockchip_pll_set_rate(&rk3328_pll_clks[clk->id - 1], in rk3328_clk_set_rate()
877 priv->cru, clk->id - 1, rate); in rk3328_clk_set_rate()
881 priv->cru, CPLL, rate); in rk3328_clk_set_rate()
882 priv->cpll_hz = rate; in rk3328_clk_set_rate()
886 priv->cru, GPLL, rate); in rk3328_clk_set_rate()
887 priv->gpll_hz = rate; in rk3328_clk_set_rate()
890 if (priv->armclk_hz) in rk3328_clk_set_rate()
892 priv->armclk_hz = rate; in rk3328_clk_set_rate()
897 rate = rk3328_bus_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
902 rate = rk3328_peri_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
908 ret = rk3328_mmc_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
918 ret = rk3328_i2c_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
924 ret = rk3328_gmac2phy_set_clk(priv->cru, rate); in rk3328_clk_set_rate()
927 ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate); in rk3328_clk_set_rate()
945 rate = rk3328_vop_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
948 rate = rk3328_crypto_set_clk(priv, clk->id, rate); in rk3328_clk_set_rate()
975 return -ENOENT; in rk3328_clk_set_rate()
982 static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent) in rk3328_gmac2io_set_parent() argument
991 * If the requested parent is in the same clock-controller and the id in rk3328_gmac2io_set_parent()
994 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) { in rk3328_gmac2io_set_parent()
996 rk_clrreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
1001 * Otherwise, we need to check the clock-output-names of the in rk3328_gmac2io_set_parent()
1004 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3328_gmac2io_set_parent()
1005 parent->id, &clock_output_name); in rk3328_gmac2io_set_parent()
1007 return -ENODATA; in rk3328_gmac2io_set_parent()
1012 rk_setreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
1016 return -EINVAL; in rk3328_gmac2io_set_parent()
1019 static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent) in rk3328_gmac2io_ext_set_parent() argument
1028 * If the requested parent is in the same clock-controller and the id in rk3328_gmac2io_ext_set_parent()
1031 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) { in rk3328_gmac2io_ext_set_parent()
1033 rk_clrreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
1038 * Otherwise, we need to check the clock-output-names of the in rk3328_gmac2io_ext_set_parent()
1041 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3328_gmac2io_ext_set_parent()
1042 parent->id, &clock_output_name); in rk3328_gmac2io_ext_set_parent()
1044 return -ENODATA; in rk3328_gmac2io_ext_set_parent()
1049 rk_setreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
1053 return -EINVAL; in rk3328_gmac2io_ext_set_parent()
1056 static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent) in rk3328_gmac2phy_set_parent() argument
1065 * If the requested parent is in the same clock-controller and the id in rk3328_gmac2phy_set_parent()
1068 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) { in rk3328_gmac2phy_set_parent()
1069 debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__); in rk3328_gmac2phy_set_parent()
1070 rk_clrreg(&grf->mac_con[2], BIT(10)); in rk3328_gmac2phy_set_parent()
1075 * Otherwise, we need to check the clock-output-names of the in rk3328_gmac2phy_set_parent()
1078 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3328_gmac2phy_set_parent()
1079 parent->id, &clock_output_name); in rk3328_gmac2phy_set_parent()
1081 return -ENODATA; in rk3328_gmac2phy_set_parent()
1085 debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__); in rk3328_gmac2phy_set_parent()
1086 rk_setreg(&grf->mac_con[2], BIT(10)); in rk3328_gmac2phy_set_parent()
1090 return -EINVAL; in rk3328_gmac2phy_set_parent()
1093 static int rk3328_lcdc_set_parent(struct clk *clk, struct clk *parent) in rk3328_lcdc_set_parent() argument
1095 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); in rk3328_lcdc_set_parent()
1097 if (parent->id == HDMIPHY) in rk3328_lcdc_set_parent()
1098 rk_clrsetreg(&priv->cru->clksel_con[40], in rk3328_lcdc_set_parent()
1101 else if (parent->id == PLL_CPLL) in rk3328_lcdc_set_parent()
1102 rk_clrsetreg(&priv->cru->clksel_con[40], in rk3328_lcdc_set_parent()
1108 rk_clrsetreg(&priv->cru->clksel_con[40], in rk3328_lcdc_set_parent()
1118 static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) in rk3328_clk_set_parent() argument
1120 switch (clk->id) { in rk3328_clk_set_parent()
1123 return rk3328_gmac2io_set_parent(clk, parent); in rk3328_clk_set_parent()
1125 return rk3328_gmac2io_ext_set_parent(clk, parent); in rk3328_clk_set_parent()
1127 return rk3328_gmac2phy_set_parent(clk, parent); in rk3328_clk_set_parent()
1129 return rk3328_lcdc_set_parent(clk, parent); in rk3328_clk_set_parent()
1139 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3328_clk_set_parent()
1140 return -ENOENT; in rk3328_clk_set_parent()
1150 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1155 int rk3328_mmc_get_phase(struct clk *clk) in rk3328_mmc_get_phase() argument
1157 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); in rk3328_mmc_get_phase()
1158 struct rk3328_cru *cru = priv->cru; in rk3328_mmc_get_phase()
1163 rate = rk3328_clk_get_rate(clk); in rk3328_mmc_get_phase()
1168 if (clk->id == SCLK_EMMC_SAMPLE) in rk3328_mmc_get_phase()
1169 raw_value = readl(&cru->emmc_con[1]); in rk3328_mmc_get_phase()
1170 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk3328_mmc_get_phase()
1171 raw_value = readl(&cru->sdmmc_con[1]); in rk3328_mmc_get_phase()
1173 raw_value = readl(&cru->sdio_con[1]); in rk3328_mmc_get_phase()
1191 int rk3328_mmc_set_phase(struct clk *clk, u32 degrees) in rk3328_mmc_set_phase() argument
1193 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); in rk3328_mmc_set_phase()
1194 struct rk3328_cru *cru = priv->cru; in rk3328_mmc_set_phase()
1199 rate = rk3328_clk_get_rate(clk); in rk3328_mmc_set_phase()
1209 * don't overflow 32-bit / 64-bit numbers. in rk3328_mmc_set_phase()
1223 if (clk->id == SCLK_EMMC_SAMPLE) in rk3328_mmc_set_phase()
1224 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rk3328_mmc_set_phase()
1225 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk3328_mmc_set_phase()
1226 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk3328_mmc_set_phase()
1228 writel(raw_value | 0xffff0000, &cru->sdio_con[1]); in rk3328_mmc_set_phase()
1231 degrees, delay_num, raw_value, rk3328_mmc_get_phase(clk)); in rk3328_mmc_set_phase()
1236 static int rk3328_clk_get_phase(struct clk *clk) in rk3328_clk_get_phase() argument
1240 debug("%s %ld\n", __func__, clk->id); in rk3328_clk_get_phase()
1241 switch (clk->id) { in rk3328_clk_get_phase()
1245 ret = rk3328_mmc_get_phase(clk); in rk3328_clk_get_phase()
1248 return -ENOENT; in rk3328_clk_get_phase()
1254 static int rk3328_clk_set_phase(struct clk *clk, int degrees) in rk3328_clk_set_phase() argument
1258 debug("%s %ld\n", __func__, clk->id); in rk3328_clk_set_phase()
1259 switch (clk->id) { in rk3328_clk_set_phase()
1263 ret = rk3328_mmc_set_phase(clk, degrees); in rk3328_clk_set_phase()
1266 return -ENOENT; in rk3328_clk_set_phase()
1283 priv->cru, NPLL) != APLL_HZ) in rkclk_init()
1286 priv->gpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[GPLL], in rkclk_init()
1287 priv->cru, GPLL); in rkclk_init()
1288 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1289 priv->cru, CPLL); in rkclk_init()
1291 /* before set pll set child div first */ in rkclk_init()
1292 rk_clrsetreg(&priv->cru->clksel_con[24], (0x3f << 8) | (0x3f << 0), in rkclk_init()
1294 rk_clrsetreg(&priv->cru->clksel_con[27], (0x1f << 8) | (0x1f << 0), in rkclk_init()
1296 rk_clrsetreg(&priv->cru->clksel_con[31], 0xff << 0, 0xb << 0); in rkclk_init()
1297 rk_clrsetreg(&priv->cru->clksel_con[43], 0xff << 0, 0xb << 0); in rkclk_init()
1298 rk_clrsetreg(&priv->cru->clksel_con[52], 0x1f << 8, 0x5 << 8); in rkclk_init()
1301 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
1302 priv->gpll_hz = GPLL_HZ; in rkclk_init()
1305 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
1306 priv->cpll_hz = CPLL_HZ; in rkclk_init()
1317 rk_clrsetreg(&priv->cru->misc, (0x1 << 13) | in rkclk_init()
1326 priv->sync_kernel = false; in rk3328_clk_probe()
1327 if (!priv->armclk_enter_hz) in rk3328_clk_probe()
1328 priv->armclk_enter_hz = in rk3328_clk_probe()
1330 priv->cru, NPLL); in rk3328_clk_probe()
1332 if (!priv->armclk_init_hz) in rk3328_clk_probe()
1333 priv->armclk_init_hz = in rk3328_clk_probe()
1335 priv->cru, NPLL); in rk3328_clk_probe()
1341 priv->sync_kernel = true; in rk3328_clk_probe()
1350 priv->cru = dev_read_addr_ptr(dev); in rk3328_clk_ofdata_to_platdata()
1369 priv->glb_srst_fst_value = offsetof(struct rk3328_cru, in rk3328_clk_bind()
1371 priv->glb_srst_snd_value = offsetof(struct rk3328_cru, in rk3328_clk_bind()
1373 sys_child->priv = priv; in rk3328_clk_bind()
1382 sf_priv->sf_reset_offset = offsetof(struct rk3328_cru, in rk3328_clk_bind()
1384 sf_priv->sf_reset_num = 12; in rk3328_clk_bind()
1385 sf_child->priv = sf_priv; in rk3328_clk_bind()
1392 { .compatible = "rockchip,rk3328-cru" },
1409 * soc_clk_dump() - Print clock frequencies
1412 * Implementation for the clk dump command.
1419 struct clk clk; in soc_clk_dump() local
1433 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1434 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1435 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1436 priv->armclk_init_hz / 1000, in soc_clk_dump()
1437 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1438 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1441 if (clk_dump->name) { in soc_clk_dump()
1442 clk.id = clk_dump->id; in soc_clk_dump()
1443 if (clk_dump->is_cru) in soc_clk_dump()
1444 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1448 rate = clk_get_rate(&clk); in soc_clk_dump()
1449 clk_free(&clk); in soc_clk_dump()
1452 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1455 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1459 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1462 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()