Lines Matching refs:vpll0_hz
188 if (!priv->vpll0_hz) in rk3308_clk_get_pll_rate()
189 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
333 return DIV_TO_RATE(priv->vpll0_hz, div) / 2; in rk3308_mmc_get_clk()
359 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate); in rk3308_mmc_set_clk()
543 parent = priv->vpll0_hz; in rk3308_vop_get_clk()
546 parent = priv->vpll0_hz; in rk3308_vop_get_clk()
573 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
745 u32 div, con, parent = priv->vpll0_hz; in rk3308_audio_get_clk()
769 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_audio_set_clk()
806 parent = priv->vpll0_hz; in rk3308_crypto_get_clk()
811 parent = priv->vpll0_hz; in rk3308_crypto_get_clk()
826 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_crypto_set_clk()
904 parent = priv->vpll0_hz; in rk3308_sclk_sfc_get_clk()
918 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_sclk_sfc_set_clk()