Lines Matching refs:dpll_hz
185 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
186 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
223 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
232 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
460 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
469 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
504 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
513 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
540 parent = priv->dpll_hz; in rk3308_vop_get_clk()
570 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
618 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
647 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_bus_set_clk()
682 u32 div, con, parent = priv->dpll_hz; in rk3308_peri_get_clk()
710 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_peri_set_clk()
902 parent = priv->dpll_hz; in rk3308_sclk_sfc_get_clk()
1026 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_set_rate()