Lines Matching +full:clk +full:- +full:div
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
18 #include <dt-bindings/clock/rk3308-cru.h>
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
89 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
139 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk()
146 return -EINVAL; in rk3308_armclk_set_clk()
155 priv->cru, APLL); in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
159 return -EINVAL; in rk3308_armclk_set_clk()
160 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
163 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
164 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
168 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
171 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
172 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
177 return -EINVAL; in rk3308_armclk_set_clk()
180 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
185 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
186 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_pll_rate()
187 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
188 if (!priv->vpll0_hz) in rk3308_clk_get_pll_rate()
189 priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_pll_rate()
190 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
191 if (!priv->vpll1_hz) in rk3308_clk_get_pll_rate()
192 priv->vpll1_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_clk_get_pll_rate()
193 priv->cru, VPLL1); in rk3308_clk_get_pll_rate()
196 static ulong rk3308_i2c_get_clk(struct clk *clk) in rk3308_i2c_get_clk() argument
198 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_i2c_get_clk()
199 struct rk3308_cru *cru = priv->cru; in rk3308_i2c_get_clk()
200 u32 div, con, con_id; in rk3308_i2c_get_clk() local
202 switch (clk->id) { in rk3308_i2c_get_clk()
217 return -EINVAL; in rk3308_i2c_get_clk()
220 con = readl(&cru->clksel_con[con_id]); in rk3308_i2c_get_clk()
221 div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3308_i2c_get_clk()
223 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
226 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) in rk3308_i2c_set_clk() argument
228 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_i2c_set_clk()
229 struct rk3308_cru *cru = priv->cru; in rk3308_i2c_set_clk()
232 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
233 assert(src_clk_div - 1 <= 127); in rk3308_i2c_set_clk()
235 switch (clk->id) { in rk3308_i2c_set_clk()
250 return -EINVAL; in rk3308_i2c_set_clk()
252 rk_clrsetreg(&cru->clksel_con[con_id], in rk3308_i2c_set_clk()
255 (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT); in rk3308_i2c_set_clk()
257 return rk3308_i2c_get_clk(clk); in rk3308_i2c_set_clk()
260 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz) in rk3308_mac_set_clk() argument
262 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mac_set_clk()
263 struct rk3308_cru *cru = priv->cru; in rk3308_mac_set_clk()
264 u32 con = readl(&cru->clksel_con[43]); in rk3308_mac_set_clk()
266 u8 div; in rk3308_mac_set_clk() local
270 priv->cru, VPLL0); in rk3308_mac_set_clk()
273 priv->cru, VPLL1); in rk3308_mac_set_clk()
276 priv->cru, DPLL); in rk3308_mac_set_clk()
282 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
283 assert(div < 32); in rk3308_mac_set_clk()
284 rk_clrsetreg(&cru->clksel_con[43], MAC_DIV_MASK, in rk3308_mac_set_clk()
285 div << MAC_DIV_SHIFT); in rk3308_mac_set_clk()
287 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
290 static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz) in rk3308_mac_set_speed_clk() argument
292 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mac_set_speed_clk()
293 struct rk3308_cru *cru = priv->cru; in rk3308_mac_set_speed_clk()
297 return -EINVAL; in rk3308_mac_set_speed_clk()
300 rk_clrsetreg(&cru->clksel_con[43], MAC_CLK_SPEED_SEL_MASK, in rk3308_mac_set_speed_clk()
306 static ulong rk3308_mmc_get_clk(struct clk *clk) in rk3308_mmc_get_clk() argument
308 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mmc_get_clk()
309 struct rk3308_cru *cru = priv->cru; in rk3308_mmc_get_clk()
310 u32 div, con, con_id; in rk3308_mmc_get_clk() local
312 switch (clk->id) { in rk3308_mmc_get_clk()
323 return -EINVAL; in rk3308_mmc_get_clk()
326 con = readl(&cru->clksel_con[con_id]); in rk3308_mmc_get_clk()
327 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rk3308_mmc_get_clk()
331 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk3308_mmc_get_clk()
333 return DIV_TO_RATE(priv->vpll0_hz, div) / 2; in rk3308_mmc_get_clk()
336 static ulong rk3308_mmc_set_clk(struct clk *clk, ulong set_rate) in rk3308_mmc_set_clk() argument
338 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mmc_set_clk()
339 struct rk3308_cru *cru = priv->cru; in rk3308_mmc_set_clk()
343 debug("%s %ld %ld\n", __func__, clk->id, set_rate); in rk3308_mmc_set_clk()
345 switch (clk->id) { in rk3308_mmc_set_clk()
355 return -EINVAL; in rk3308_mmc_set_clk()
358 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rk3308_mmc_set_clk()
359 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate); in rk3308_mmc_set_clk()
364 rk_clrsetreg(&cru->clksel_con[con_id], in rk3308_mmc_set_clk()
368 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
370 rk_clrsetreg(&cru->clksel_con[con_id], in rk3308_mmc_set_clk()
374 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
377 return rk3308_mmc_get_clk(clk); in rk3308_mmc_set_clk()
380 static ulong rk3308_saradc_get_clk(struct clk *clk) in rk3308_saradc_get_clk() argument
382 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_saradc_get_clk()
383 struct rk3308_cru *cru = priv->cru; in rk3308_saradc_get_clk()
384 u32 div, con; in rk3308_saradc_get_clk() local
386 con = readl(&cru->clksel_con[34]); in rk3308_saradc_get_clk()
387 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in rk3308_saradc_get_clk()
389 return DIV_TO_RATE(OSC_HZ, div); in rk3308_saradc_get_clk()
392 static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz) in rk3308_saradc_set_clk() argument
394 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_saradc_set_clk()
395 struct rk3308_cru *cru = priv->cru; in rk3308_saradc_set_clk()
399 assert(src_clk_div - 1 <= 2047); in rk3308_saradc_set_clk()
401 rk_clrsetreg(&cru->clksel_con[34], in rk3308_saradc_set_clk()
403 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk3308_saradc_set_clk()
405 return rk3308_saradc_get_clk(clk); in rk3308_saradc_set_clk()
408 static ulong rk3308_tsadc_get_clk(struct clk *clk) in rk3308_tsadc_get_clk() argument
410 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_tsadc_get_clk()
411 struct rk3308_cru *cru = priv->cru; in rk3308_tsadc_get_clk()
412 u32 div, con; in rk3308_tsadc_get_clk() local
414 con = readl(&cru->clksel_con[33]); in rk3308_tsadc_get_clk()
415 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in rk3308_tsadc_get_clk()
417 return DIV_TO_RATE(OSC_HZ, div); in rk3308_tsadc_get_clk()
420 static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz) in rk3308_tsadc_set_clk() argument
422 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_tsadc_set_clk()
423 struct rk3308_cru *cru = priv->cru; in rk3308_tsadc_set_clk()
427 assert(src_clk_div - 1 <= 2047); in rk3308_tsadc_set_clk()
429 rk_clrsetreg(&cru->clksel_con[33], in rk3308_tsadc_set_clk()
431 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk3308_tsadc_set_clk()
433 return rk3308_tsadc_get_clk(clk); in rk3308_tsadc_set_clk()
436 static ulong rk3308_spi_get_clk(struct clk *clk) in rk3308_spi_get_clk() argument
438 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_spi_get_clk()
439 struct rk3308_cru *cru = priv->cru; in rk3308_spi_get_clk()
440 u32 div, con, con_id; in rk3308_spi_get_clk() local
442 switch (clk->id) { in rk3308_spi_get_clk()
454 return -EINVAL; in rk3308_spi_get_clk()
457 con = readl(&cru->clksel_con[con_id]); in rk3308_spi_get_clk()
458 div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; in rk3308_spi_get_clk()
460 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
463 static ulong rk3308_spi_set_clk(struct clk *clk, uint hz) in rk3308_spi_set_clk() argument
465 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_spi_set_clk()
466 struct rk3308_cru *cru = priv->cru; in rk3308_spi_set_clk()
469 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
470 assert(src_clk_div - 1 <= 127); in rk3308_spi_set_clk()
472 switch (clk->id) { in rk3308_spi_set_clk()
484 return -EINVAL; in rk3308_spi_set_clk()
487 rk_clrsetreg(&cru->clksel_con[con_id], in rk3308_spi_set_clk()
490 (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT); in rk3308_spi_set_clk()
492 return rk3308_spi_get_clk(clk); in rk3308_spi_set_clk()
495 static ulong rk3308_pwm_get_clk(struct clk *clk) in rk3308_pwm_get_clk() argument
497 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_pwm_get_clk()
498 struct rk3308_cru *cru = priv->cru; in rk3308_pwm_get_clk()
499 u32 div, con; in rk3308_pwm_get_clk() local
501 con = readl(&cru->clksel_con[29]); in rk3308_pwm_get_clk()
502 div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; in rk3308_pwm_get_clk()
504 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
507 static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz) in rk3308_pwm_set_clk() argument
509 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_pwm_set_clk()
510 struct rk3308_cru *cru = priv->cru; in rk3308_pwm_set_clk()
513 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
514 assert(src_clk_div - 1 <= 127); in rk3308_pwm_set_clk()
516 rk_clrsetreg(&cru->clksel_con[29], in rk3308_pwm_set_clk()
519 (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); in rk3308_pwm_set_clk()
521 return rk3308_pwm_get_clk(clk); in rk3308_pwm_set_clk()
524 static ulong rk3308_vop_get_clk(struct clk *clk) in rk3308_vop_get_clk() argument
526 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_vop_get_clk()
527 struct rk3308_cru *cru = priv->cru; in rk3308_vop_get_clk()
528 u32 div, pll_sel, vol_sel, con, parent; in rk3308_vop_get_clk() local
530 con = readl(&cru->clksel_con[8]); in rk3308_vop_get_clk()
533 div = con & DCLK_VOP_DIV_MASK; in rk3308_vop_get_clk()
540 parent = priv->dpll_hz; in rk3308_vop_get_clk()
543 parent = priv->vpll0_hz; in rk3308_vop_get_clk()
546 parent = priv->vpll0_hz; in rk3308_vop_get_clk()
550 return -EINVAL; in rk3308_vop_get_clk()
554 return -EINVAL; in rk3308_vop_get_clk()
557 return DIV_TO_RATE(parent, div); in rk3308_vop_get_clk()
560 static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz) in rk3308_vop_set_clk() argument
562 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_vop_set_clk()
563 struct rk3308_cru *cru = priv->cru; in rk3308_vop_set_clk()
565 u32 i, div, best_div = 0, best_sel = 0; in rk3308_vop_set_clk() local
570 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
573 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
576 pll_rate = priv->vpll1_hz; in rk3308_vop_set_clk()
580 return -EINVAL; in rk3308_vop_set_clk()
583 div = DIV_ROUND_UP(pll_rate, hz); in rk3308_vop_set_clk()
584 if (div > 255) in rk3308_vop_set_clk()
586 now = pll_rate / div; in rk3308_vop_set_clk()
587 if (abs(hz - now) < abs(hz - best_rate)) { in rk3308_vop_set_clk()
589 best_div = div; in rk3308_vop_set_clk()
597 rk_clrsetreg(&cru->clksel_con[8], in rk3308_vop_set_clk()
601 rk_clrsetreg(&cru->clksel_con[8], in rk3308_vop_set_clk()
606 (best_div - 1) << DCLK_VOP_DIV_SHIFT); in rk3308_vop_set_clk()
609 return -EINVAL; in rk3308_vop_set_clk()
612 return rk3308_vop_get_clk(clk); in rk3308_vop_set_clk()
617 struct rk3308_cru *cru = priv->cru; in rk3308_bus_get_clk()
618 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() local
622 con = readl(&cru->clksel_con[5]); in rk3308_bus_get_clk()
623 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; in rk3308_bus_get_clk()
626 con = readl(&cru->clksel_con[6]); in rk3308_bus_get_clk()
627 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; in rk3308_bus_get_clk()
631 con = readl(&cru->clksel_con[6]); in rk3308_bus_get_clk()
632 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; in rk3308_bus_get_clk()
635 return -ENOENT; in rk3308_bus_get_clk()
638 return DIV_TO_RATE(parent, div); in rk3308_bus_get_clk()
644 struct rk3308_cru *cru = priv->cru; in rk3308_bus_set_clk()
647 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_bus_set_clk()
648 assert(src_clk_div - 1 <= 31); in rk3308_bus_set_clk()
656 rk_clrsetreg(&cru->clksel_con[5], in rk3308_bus_set_clk()
659 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); in rk3308_bus_set_clk()
662 rk_clrsetreg(&cru->clksel_con[6], in rk3308_bus_set_clk()
664 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); in rk3308_bus_set_clk()
667 rk_clrsetreg(&cru->clksel_con[6], in rk3308_bus_set_clk()
669 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); in rk3308_bus_set_clk()
673 return -EINVAL; in rk3308_bus_set_clk()
681 struct rk3308_cru *cru = priv->cru; in rk3308_peri_get_clk()
682 u32 div, con, parent = priv->dpll_hz; in rk3308_peri_get_clk() local
686 con = readl(&cru->clksel_con[36]); in rk3308_peri_get_clk()
687 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; in rk3308_peri_get_clk()
690 con = readl(&cru->clksel_con[37]); in rk3308_peri_get_clk()
691 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; in rk3308_peri_get_clk()
694 con = readl(&cru->clksel_con[37]); in rk3308_peri_get_clk()
695 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT; in rk3308_peri_get_clk()
698 return -ENOENT; in rk3308_peri_get_clk()
701 return DIV_TO_RATE(parent, div); in rk3308_peri_get_clk()
707 struct rk3308_cru *cru = priv->cru; in rk3308_peri_set_clk()
710 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_peri_set_clk()
711 assert(src_clk_div - 1 <= 31); in rk3308_peri_set_clk()
719 rk_clrsetreg(&cru->clksel_con[36], in rk3308_peri_set_clk()
722 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in rk3308_peri_set_clk()
725 rk_clrsetreg(&cru->clksel_con[37], in rk3308_peri_set_clk()
727 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); in rk3308_peri_set_clk()
730 rk_clrsetreg(&cru->clksel_con[37], in rk3308_peri_set_clk()
732 (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT); in rk3308_peri_set_clk()
736 return -EINVAL; in rk3308_peri_set_clk()
744 struct rk3308_cru *cru = priv->cru; in rk3308_audio_get_clk()
745 u32 div, con, parent = priv->vpll0_hz; in rk3308_audio_get_clk() local
749 con = readl(&cru->clksel_con[45]); in rk3308_audio_get_clk()
750 div = (con & AUDIO_HCLK_DIV_MASK) >> AUDIO_HCLK_DIV_SHIFT; in rk3308_audio_get_clk()
753 con = readl(&cru->clksel_con[45]); in rk3308_audio_get_clk()
754 div = (con & AUDIO_PCLK_DIV_MASK) >> AUDIO_PCLK_DIV_SHIFT; in rk3308_audio_get_clk()
757 return -ENOENT; in rk3308_audio_get_clk()
760 return DIV_TO_RATE(parent, div); in rk3308_audio_get_clk()
766 struct rk3308_cru *cru = priv->cru; in rk3308_audio_set_clk()
769 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_audio_set_clk()
770 assert(src_clk_div - 1 <= 31); in rk3308_audio_set_clk()
778 rk_clrsetreg(&cru->clksel_con[45], in rk3308_audio_set_clk()
781 (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT); in rk3308_audio_set_clk()
784 rk_clrsetreg(&cru->clksel_con[45], in rk3308_audio_set_clk()
787 (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT); in rk3308_audio_set_clk()
791 return -EINVAL; in rk3308_audio_set_clk()
799 struct rk3308_cru *cru = priv->cru; in rk3308_crypto_get_clk()
800 u32 div, con, parent; in rk3308_crypto_get_clk() local
804 con = readl(&cru->clksel_con[7]); in rk3308_crypto_get_clk()
805 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in rk3308_crypto_get_clk()
806 parent = priv->vpll0_hz; in rk3308_crypto_get_clk()
809 con = readl(&cru->clksel_con[7]); in rk3308_crypto_get_clk()
810 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; in rk3308_crypto_get_clk()
811 parent = priv->vpll0_hz; in rk3308_crypto_get_clk()
814 return -ENOENT; in rk3308_crypto_get_clk()
817 return DIV_TO_RATE(parent, div); in rk3308_crypto_get_clk()
823 struct rk3308_cru *cru = priv->cru; in rk3308_crypto_set_clk()
826 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_crypto_set_clk()
827 assert(src_clk_div - 1 <= 31); in rk3308_crypto_set_clk()
835 rk_clrsetreg(&cru->clksel_con[7], in rk3308_crypto_set_clk()
838 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk3308_crypto_set_clk()
841 rk_clrsetreg(&cru->clksel_con[7], in rk3308_crypto_set_clk()
844 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in rk3308_crypto_set_clk()
848 return -EINVAL; in rk3308_crypto_set_clk()
856 struct rk3308_cru *cru = priv->cru; in rk3308_rtc32k_get_clk()
860 con = readl(&cru->clksel_con[2]); in rk3308_rtc32k_get_clk()
863 return -EINVAL; in rk3308_rtc32k_get_clk()
865 fracdiv = readl(&cru->clksel_con[3]); in rk3308_rtc32k_get_clk()
877 struct rk3308_cru *cru = priv->cru; in rk3308_rtc32k_set_clk()
881 GENMASK(16 - 1, 0), in rk3308_rtc32k_set_clk()
882 GENMASK(16 - 1, 0), in rk3308_rtc32k_set_clk()
885 writel(val, &cru->clksel_con[3]); in rk3308_rtc32k_set_clk()
886 rk_clrsetreg(&cru->clksel_con[2], CLK_RTC32K_SEL_MASK, in rk3308_rtc32k_set_clk()
894 struct rk3308_cru *cru = priv->cru; in rk3308_sclk_sfc_get_clk()
895 u32 div, con, sel, parent; in rk3308_sclk_sfc_get_clk() local
897 con = readl(&cru->clksel_con[42]); in rk3308_sclk_sfc_get_clk()
898 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rk3308_sclk_sfc_get_clk()
902 parent = priv->dpll_hz; in rk3308_sclk_sfc_get_clk()
904 parent = priv->vpll0_hz; in rk3308_sclk_sfc_get_clk()
906 parent = priv->vpll1_hz; in rk3308_sclk_sfc_get_clk()
908 return -EINVAL; in rk3308_sclk_sfc_get_clk()
910 return DIV_TO_RATE(parent, div); in rk3308_sclk_sfc_get_clk()
915 struct rk3308_cru *cru = priv->cru; in rk3308_sclk_sfc_set_clk()
918 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_sclk_sfc_set_clk()
919 assert(src_clk_div - 1 <= 127); in rk3308_sclk_sfc_set_clk()
921 rk_clrsetreg(&cru->clksel_con[42], in rk3308_sclk_sfc_set_clk()
924 (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); in rk3308_sclk_sfc_set_clk()
929 static ulong rk3308_clk_get_rate(struct clk *clk) in rk3308_clk_get_rate() argument
931 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_clk_get_rate()
934 debug("%s id:%ld\n", __func__, clk->id); in rk3308_clk_get_rate()
936 switch (clk->id) { in rk3308_clk_get_rate()
940 priv->cru, APLL); in rk3308_clk_get_rate()
944 priv->cru, DPLL); in rk3308_clk_get_rate()
948 priv->cru, VPLL0); in rk3308_clk_get_rate()
952 priv->cru, VPLL1); in rk3308_clk_get_rate()
959 rate = rk3308_mmc_get_clk(clk); in rk3308_clk_get_rate()
965 rate = rk3308_i2c_get_clk(clk); in rk3308_clk_get_rate()
968 rate = rk3308_saradc_get_clk(clk); in rk3308_clk_get_rate()
971 rate = rk3308_tsadc_get_clk(clk); in rk3308_clk_get_rate()
975 rate = rk3308_spi_get_clk(clk); in rk3308_clk_get_rate()
978 rate = rk3308_pwm_get_clk(clk); in rk3308_clk_get_rate()
981 rate = rk3308_vop_get_clk(clk); in rk3308_clk_get_rate()
987 rate = rk3308_bus_get_clk(priv, clk->id); in rk3308_clk_get_rate()
992 rate = rk3308_peri_get_clk(priv, clk->id); in rk3308_clk_get_rate()
996 rate = rk3308_audio_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1000 rate = rk3308_crypto_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1003 rate = rk3308_rtc32k_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1009 return -ENOENT; in rk3308_clk_get_rate()
1015 static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) in rk3308_clk_set_rate() argument
1017 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_clk_set_rate()
1020 debug("%s %ld %ld\n", __func__, clk->id, rate); in rk3308_clk_set_rate()
1022 switch (clk->id) { in rk3308_clk_set_rate()
1024 ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru, in rk3308_clk_set_rate()
1026 priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_set_rate()
1027 priv->cru, DPLL); in rk3308_clk_set_rate()
1030 if (priv->armclk_hz) in rk3308_clk_set_rate()
1032 priv->armclk_hz = rate; in rk3308_clk_set_rate()
1038 ret = rk3308_mmc_set_clk(clk, rate); in rk3308_clk_set_rate()
1044 ret = rk3308_i2c_set_clk(clk, rate); in rk3308_clk_set_rate()
1047 ret = rk3308_mac_set_clk(clk, rate); in rk3308_clk_set_rate()
1050 ret = rk3308_mac_set_speed_clk(clk, rate); in rk3308_clk_set_rate()
1053 ret = rk3308_saradc_set_clk(clk, rate); in rk3308_clk_set_rate()
1056 ret = rk3308_tsadc_set_clk(clk, rate); in rk3308_clk_set_rate()
1060 ret = rk3308_spi_set_clk(clk, rate); in rk3308_clk_set_rate()
1063 ret = rk3308_pwm_set_clk(clk, rate); in rk3308_clk_set_rate()
1066 ret = rk3308_vop_set_clk(clk, rate); in rk3308_clk_set_rate()
1071 rate = rk3308_bus_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1076 rate = rk3308_peri_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1080 rate = rk3308_audio_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1084 ret = rk3308_crypto_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1087 ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1093 return -ENOENT; in rk3308_clk_set_rate()
1107 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1112 int rockchip_mmc_get_phase(struct clk *clk) in rockchip_mmc_get_phase() argument
1114 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_get_phase()
1115 struct rk3308_cru *cru = priv->cru; in rockchip_mmc_get_phase()
1120 rate = rk3308_clk_get_rate(clk); in rockchip_mmc_get_phase()
1125 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_get_phase()
1126 raw_value = readl(&cru->emmc_con[1]); in rockchip_mmc_get_phase()
1128 raw_value = readl(&cru->sdmmc_con[1]); in rockchip_mmc_get_phase()
1147 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) in rockchip_mmc_set_phase() argument
1149 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_set_phase()
1150 struct rk3308_cru *cru = priv->cru; in rockchip_mmc_set_phase()
1155 rate = rk3308_clk_get_rate(clk); in rockchip_mmc_set_phase()
1165 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
1178 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_set_phase()
1179 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rockchip_mmc_set_phase()
1181 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rockchip_mmc_set_phase()
1184 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); in rockchip_mmc_set_phase()
1190 static int rk3308_clk_get_phase(struct clk *clk) in rk3308_clk_get_phase() argument
1194 switch (clk->id) { in rk3308_clk_get_phase()
1197 ret = rockchip_mmc_get_phase(clk); in rk3308_clk_get_phase()
1200 return -ENOENT; in rk3308_clk_get_phase()
1206 static int rk3308_clk_set_phase(struct clk *clk, int degrees) in rk3308_clk_set_phase() argument
1210 switch (clk->id) { in rk3308_clk_set_phase()
1213 ret = rockchip_mmc_set_phase(clk, degrees); in rk3308_clk_set_phase()
1216 return -ENOENT; in rk3308_clk_set_phase()
1222 static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent) in rk3308_mac_set_parent() argument
1224 struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); in rk3308_mac_set_parent()
1227 * If the requested parent is in the same clock-controller and in rk3308_mac_set_parent()
1230 if (parent->id == SCLK_MAC_SRC) { in rk3308_mac_set_parent()
1232 rk_clrreg(&priv->cru->clksel_con[43], BIT(14)); in rk3308_mac_set_parent()
1235 rk_setreg(&priv->cru->clksel_con[43], BIT(14)); in rk3308_mac_set_parent()
1241 static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *parent) in rk3308_clk_set_parent() argument
1243 switch (clk->id) { in rk3308_clk_set_parent()
1245 return rk3308_mac_set_parent(clk, parent); in rk3308_clk_set_parent()
1250 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3308_clk_set_parent()
1251 return -ENOENT; in rk3308_clk_set_parent()
1270 priv->cru, APLL) != APLL_HZ) { in rk3308_clk_init()
1295 priv->sync_kernel = false; in rk3308_clk_probe()
1296 if (!priv->armclk_enter_hz) in rk3308_clk_probe()
1297 priv->armclk_enter_hz = in rk3308_clk_probe()
1299 priv->cru, APLL); in rk3308_clk_probe()
1301 if (!priv->armclk_init_hz) in rk3308_clk_probe()
1302 priv->armclk_init_hz = in rk3308_clk_probe()
1304 priv->cru, APLL); in rk3308_clk_probe()
1306 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk3308_clk_probe()
1311 priv->sync_kernel = true; in rk3308_clk_probe()
1320 priv->cru = dev_read_addr_ptr(dev); in rk3308_clk_ofdata_to_platdata()
1339 priv->glb_srst_fst_value = offsetof(struct rk3308_cru, in rk3308_clk_bind()
1341 priv->glb_srst_snd_value = offsetof(struct rk3308_cru, in rk3308_clk_bind()
1343 sys_child->priv = priv; in rk3308_clk_bind()
1352 sf_priv->sf_reset_offset = offsetof(struct rk3308_cru, in rk3308_clk_bind()
1354 sf_priv->sf_reset_num = 12; in rk3308_clk_bind()
1355 sf_child->priv = sf_priv; in rk3308_clk_bind()
1362 { .compatible = "rockchip,rk3308-cru" },
1378 * soc_clk_dump() - Print clock frequencies
1381 * Implementation for the clk dump command.
1388 struct clk clk; in soc_clk_dump() local
1402 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1403 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1404 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1405 priv->armclk_init_hz / 1000, in soc_clk_dump()
1406 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1407 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1410 if (clk_dump->name) { in soc_clk_dump()
1411 clk.id = clk_dump->id; in soc_clk_dump()
1412 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1416 rate = clk_get_rate(&clk); in soc_clk_dump()
1417 clk_free(&clk); in soc_clk_dump()
1420 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1423 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1427 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1430 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()