Lines Matching +full:1 +full:hz
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
46 RK3036_PLL_RATE(1300000000, 6, 325, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
48 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
49 RK3036_PLL_RATE(748000000, 2, 187, 3, 1, 1, 0),
53 RK3308_CPUCLK_RATE(1200000000, 1, 5),
54 RK3308_CPUCLK_RATE(1008000000, 1, 5),
55 RK3308_CPUCLK_RATE(816000000, 1, 3),
56 RK3308_CPUCLK_RATE(600000000, 1, 3),
57 RK3308_CPUCLK_RATE(408000000, 1, 1),
89 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
110 n1 = 1; in rational_best_approximation()
111 d0 = 1; in rational_best_approximation()
137 static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz) in rk3308_armclk_set_clk() argument
143 rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz); in rk3308_armclk_set_clk()
152 * core hz : apll = 1:1 in rk3308_armclk_set_clk()
156 if (old_rate > hz) { in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
167 } else if (old_rate < hz) { in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
226 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) in rk3308_i2c_set_clk() argument
232 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
233 assert(src_clk_div - 1 <= 127); in rk3308_i2c_set_clk()
255 (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT); in rk3308_i2c_set_clk()
260 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz) in rk3308_mac_set_clk() argument
279 if (!hz) in rk3308_mac_set_clk()
280 hz = 50000000; in rk3308_mac_set_clk()
282 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
290 static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz) in rk3308_mac_set_speed_clk() argument
295 if (hz != 2500000 && hz != 25000000) { in rk3308_mac_set_speed_clk()
296 debug("Unsupported mac speed:%d\n", hz); in rk3308_mac_set_speed_clk()
301 ((hz == 2500000) ? 0 : 1) << MAC_CLK_SPEED_SEL_SHIFT); in rk3308_mac_set_speed_clk()
368 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
374 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk3308_mmc_set_clk()
392 static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz) in rk3308_saradc_set_clk() argument
398 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_saradc_set_clk()
399 assert(src_clk_div - 1 <= 2047); in rk3308_saradc_set_clk()
403 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk3308_saradc_set_clk()
420 static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz) in rk3308_tsadc_set_clk() argument
426 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk3308_tsadc_set_clk()
427 assert(src_clk_div - 1 <= 2047); in rk3308_tsadc_set_clk()
431 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk3308_tsadc_set_clk()
463 static ulong rk3308_spi_set_clk(struct clk *clk, uint hz) in rk3308_spi_set_clk() argument
469 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
470 assert(src_clk_div - 1 <= 127); in rk3308_spi_set_clk()
490 (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT); in rk3308_spi_set_clk()
507 static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz) in rk3308_pwm_set_clk() argument
513 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
514 assert(src_clk_div - 1 <= 127); in rk3308_pwm_set_clk()
519 (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); in rk3308_pwm_set_clk()
560 static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz) in rk3308_vop_set_clk() argument
583 div = DIV_ROUND_UP(pll_rate, hz); in rk3308_vop_set_clk()
587 if (abs(hz - now) < abs(hz - best_rate)) { in rk3308_vop_set_clk()
596 if (best_rate != hz && hz == OSC_HZ) { in rk3308_vop_set_clk()
606 (best_div - 1) << DCLK_VOP_DIV_SHIFT); in rk3308_vop_set_clk()
642 ulong hz) in rk3308_bus_set_clk() argument
647 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_bus_set_clk()
648 assert(src_clk_div - 1 <= 31); in rk3308_bus_set_clk()
659 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); in rk3308_bus_set_clk()
664 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); in rk3308_bus_set_clk()
669 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); in rk3308_bus_set_clk()
705 ulong hz) in rk3308_peri_set_clk() argument
710 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_peri_set_clk()
711 assert(src_clk_div - 1 <= 31); in rk3308_peri_set_clk()
722 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in rk3308_peri_set_clk()
727 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); in rk3308_peri_set_clk()
732 (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT); in rk3308_peri_set_clk()
764 ulong hz) in rk3308_audio_set_clk() argument
769 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_audio_set_clk()
770 assert(src_clk_div - 1 <= 31); in rk3308_audio_set_clk()
781 (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT); in rk3308_audio_set_clk()
787 (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT); in rk3308_audio_set_clk()
821 ulong hz) in rk3308_crypto_set_clk() argument
826 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_crypto_set_clk()
827 assert(src_clk_div - 1 <= 31); in rk3308_crypto_set_clk()
838 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk3308_crypto_set_clk()
844 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in rk3308_crypto_set_clk()
875 ulong hz) in rk3308_rtc32k_set_clk() argument
880 rational_best_approximation(hz, OSC_HZ, in rk3308_rtc32k_set_clk()
881 GENMASK(16 - 1, 0), in rk3308_rtc32k_set_clk()
882 GENMASK(16 - 1, 0), in rk3308_rtc32k_set_clk()
913 static ulong rk3308_sclk_sfc_set_clk(struct rk3308_clk_priv *priv, uint hz) in rk3308_sclk_sfc_set_clk() argument
918 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz); in rk3308_sclk_sfc_set_clk()
919 assert(src_clk_div - 1 <= 127); in rk3308_sclk_sfc_set_clk()
924 (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); in rk3308_sclk_sfc_set_clk()
1100 #define ROCKCHIP_MMC_DEGREE_OFFSET 1
1126 raw_value = readl(&cru->emmc_con[1]); in rockchip_mmc_get_phase()
1128 raw_value = readl(&cru->sdmmc_con[1]); in rockchip_mmc_get_phase()
1179 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rockchip_mmc_set_phase()
1181 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rockchip_mmc_set_phase()