Lines Matching full:cru
20 #include <dt-bindings/clock/rk3288-cru.h>
235 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
239 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
269 static u32 rkclk_pll_get_rate(struct rk3288_cru *cru, in rkclk_pll_get_rate() argument
275 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
282 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
302 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, in rkclk_configure_ddr() argument
332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
335 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
436 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) in rockchip_mac_set_clk() argument
444 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { in rockchip_mac_set_clk()
448 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk()
463 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
474 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, in rockchip_vop_set_clk() argument
482 gpll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_vop_set_clk()
483 npll_rate = rkclk_pll_get_rate(cru, CLK_NEW); in rockchip_vop_set_clk()
488 ret = (readl(&cru->cru_clksel_con[27]) & DCLK_VOP0_PLL_MASK) >> in rockchip_vop_set_clk()
495 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
497 rkclk_set_pll(cru, CLK_CODEC, &cpll_config); in rockchip_vop_set_clk()
507 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
519 rk_clrsetreg(&cru->cru_clksel_con[27], in rockchip_vop_set_clk()
525 ret = (readl(&cru->cru_clksel_con[29]) & DCLK_VOP1_PLL_MASK) >> in rockchip_vop_set_clk()
532 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
534 rkclk_set_pll(cru, CLK_CODEC, &cpll_config); in rockchip_vop_set_clk()
544 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
557 rk_clrsetreg(&cru->cru_clksel_con[29], in rockchip_vop_set_clk()
564 rk_clrsetreg(&cru->cru_clksel_con[31], in rockchip_vop_set_clk()
571 rk_clrsetreg(&cru->cru_clksel_con[31], in rockchip_vop_set_clk()
577 rk_clrsetreg(&cru->cru_clksel_con[28], in rockchip_vop_set_clk()
587 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) in rkclk_init() argument
594 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
600 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
601 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); in rkclk_init()
623 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
646 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
654 rk_clrsetreg(&cru->cru_clksel_con[39], in rkclk_init()
658 rk_clrsetreg(&cru->cru_clksel_con[42], in rkclk_init()
667 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
673 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) in rk3288_clk_configure_cpu() argument
676 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
679 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rk3288_clk_configure_cpu()
691 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3288_clk_configure_cpu()
702 rk_clrsetreg(&cru->cru_clksel_con[37], in rk3288_clk_configure_cpu()
710 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
714 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, in rockchip_mmc_get_clk() argument
725 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
731 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
737 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
749 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, in rockchip_mmc_set_clk() argument
756 /* mmc clock default div 2 internal, need provide double in cru */ in rockchip_mmc_set_clk()
773 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
780 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
787 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
796 return rockchip_mmc_get_clk(cru, gclk_rate, periph); in rockchip_mmc_set_clk()
799 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, in rockchip_spi_get_clk() argument
807 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
812 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
817 con = readl(&cru->cru_clksel_con[39]); in rockchip_spi_get_clk()
829 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, in rockchip_spi_set_clk() argument
839 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
845 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
851 rk_clrsetreg(&cru->cru_clksel_con[39], in rockchip_spi_set_clk()
860 return rockchip_spi_get_clk(cru, gclk_rate, periph); in rockchip_spi_set_clk()
863 static ulong rockchip_aclk_peri_get_clk(struct rk3288_cru *cru) in rockchip_aclk_peri_get_clk() argument
869 con = readl(&cru->cru_clksel_con[10]); in rockchip_aclk_peri_get_clk()
873 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_peri_get_clk()
875 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_peri_get_clk()
881 static ulong rockchip_aclk_cpu_get_clk(struct rk3288_cru *cru) in rockchip_aclk_cpu_get_clk() argument
887 con = readl(&cru->cru_clksel_con[1]); in rockchip_aclk_cpu_get_clk()
891 parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rockchip_aclk_cpu_get_clk()
893 parent_rate = rkclk_pll_get_rate(cru, CLK_CODEC); in rockchip_aclk_cpu_get_clk()
902 static ulong rockchip_pclk_peri_get_clk(struct rk3288_cru *cru) in rockchip_pclk_peri_get_clk() argument
908 parent_rate = rockchip_aclk_peri_get_clk(cru); in rockchip_pclk_peri_get_clk()
909 con = readl(&cru->cru_clksel_con[10]); in rockchip_pclk_peri_get_clk()
916 static ulong rockchip_pclk_cpu_get_clk(struct rk3288_cru *cru) in rockchip_pclk_cpu_get_clk() argument
922 parent_rate = rockchip_aclk_cpu_get_clk(cru); in rockchip_pclk_cpu_get_clk()
923 con = readl(&cru->cru_clksel_con[1]); in rockchip_pclk_cpu_get_clk()
930 static ulong rockchip_i2c_get_clk(struct rk3288_cru *cru, int periph) in rockchip_i2c_get_clk() argument
935 return rockchip_pclk_cpu_get_clk(cru); in rockchip_i2c_get_clk()
940 return rockchip_pclk_peri_get_clk(cru); in rockchip_i2c_get_clk()
946 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) in rockchip_saradc_get_clk() argument
950 val = readl(&cru->cru_clksel_con[24]); in rockchip_saradc_get_clk()
957 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_saradc_set_clk() argument
964 rk_clrsetreg(&cru->cru_clksel_con[24], in rockchip_saradc_set_clk()
968 return rockchip_saradc_get_clk(cru); in rockchip_saradc_set_clk()
971 static ulong rockchip_tsadc_get_clk(struct rk3288_cru *cru) in rockchip_tsadc_get_clk() argument
975 val = readl(&cru->cru_clksel_con[2]); in rockchip_tsadc_get_clk()
982 static ulong rockchip_tsadc_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_tsadc_set_clk() argument
989 rk_clrsetreg(&cru->cru_clksel_con[2], in rockchip_tsadc_set_clk()
993 return rockchip_tsadc_get_clk(cru); in rockchip_tsadc_set_clk()
998 static ulong rockchip_crypto_get_clk(struct rk3288_cru *cru) in rockchip_crypto_get_clk() argument
1002 val = readl(&cru->cru_clksel_con[26]); in rockchip_crypto_get_clk()
1005 return DIV_TO_RATE(rockchip_aclk_cpu_get_clk(cru), div); in rockchip_crypto_get_clk()
1008 static ulong rockchip_crypto_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_crypto_set_clk() argument
1013 p_rate = rockchip_aclk_cpu_get_clk(cru); in rockchip_crypto_set_clk()
1017 rk_clrsetreg(&cru->cru_clksel_con[26], in rockchip_crypto_set_clk()
1021 return rockchip_crypto_get_clk(cru); in rockchip_crypto_set_clk()
1024 static ulong rk3288_alive_get_clk(struct rk3288_cru *cru, uint gclk_rate) in rk3288_alive_get_clk() argument
1028 con = readl(&cru->cru_clksel_con[33]); in rk3288_alive_get_clk()
1035 static ulong rockchip_test_get_clk(struct rk3288_cru *cru, int id) in rockchip_test_get_clk() argument
1039 val = readl(&cru->cru_misc_con); in rockchip_test_get_clk()
1053 static ulong rockchip_test_set_clk(struct rk3288_cru *cru, int id, uint hz) in rockchip_test_set_clk() argument
1070 rk_clrsetreg(&cru->cru_misc_con, in rockchip_test_set_clk()
1074 return rockchip_test_get_clk(cru, id); in rockchip_test_set_clk()
1083 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_get_rate()
1086 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
1096 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1101 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1109 new_rate = rockchip_i2c_get_clk(priv->cru, clk->id); in rk3288_clk_get_rate()
1115 new_rate = rockchip_saradc_get_clk(priv->cru); in rk3288_clk_get_rate()
1118 new_rate = rockchip_tsadc_get_clk(priv->cru); in rk3288_clk_get_rate()
1121 new_rate = rockchip_aclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
1124 new_rate = rockchip_aclk_peri_get_clk(priv->cru); in rk3288_clk_get_rate()
1127 new_rate = rockchip_pclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
1130 new_rate = rockchip_pclk_peri_get_clk(priv->cru); in rk3288_clk_get_rate()
1134 new_rate = rockchip_crypto_get_clk(priv->cru); in rk3288_clk_get_rate()
1137 new_rate = rk3288_alive_get_clk(priv->cru, gclk_rate); in rk3288_clk_get_rate()
1141 new_rate = rockchip_test_get_clk(priv->cru, clk->id); in rk3288_clk_get_rate()
1154 struct rk3288_cru *cru = priv->cru; in rk3288_clk_set_rate() local
1157 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_set_rate()
1163 rk3288_clk_configure_cpu(priv->cru, priv->grf); in rk3288_clk_set_rate()
1167 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); in rk3288_clk_set_rate()
1175 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
1180 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
1184 new_rate = rockchip_mac_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1190 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); in rk3288_clk_set_rate()
1194 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); in rk3288_clk_set_rate()
1197 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1199 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1204 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); in rk3288_clk_set_rate()
1207 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
1209 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
1213 new_rate = rockchip_crypto_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1217 new_rate = rockchip_test_set_clk(priv->cru, clk->id, rate); in rk3288_clk_set_rate()
1221 new_rate = rockchip_saradc_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1224 new_rate = rockchip_tsadc_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1259 struct rk3288_cru *cru = priv->cru; in rockchip_mmc_get_phase() local
1270 raw_value = readl(&cru->cru_emmc_con[1]); in rockchip_mmc_get_phase()
1272 raw_value = readl(&cru->cru_sdmmc_con[1]); in rockchip_mmc_get_phase()
1292 struct rk3288_cru *cru = priv->cru; in rockchip_mmc_set_phase() local
1321 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); in rockchip_mmc_set_phase()
1323 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); in rockchip_mmc_set_phase()
1366 struct rk3288_cru *cru = priv->cru; in rk3288_gmac_set_parent() local
1377 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); in rk3288_gmac_set_parent()
1393 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, in rk3288_gmac_set_parent()
1405 struct rk3288_cru *cru = priv->cru; in rk3288_vop_set_parent() local
1425 rk_clrsetreg(&cru->cru_clksel_con[27], in rk3288_vop_set_parent()
1429 rk_clrsetreg(&cru->cru_clksel_con[29], in rk3288_vop_set_parent()
1470 priv->cru = dev_read_addr_ptr(dev); in rk3288_clk_ofdata_to_platdata()
1489 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3288_clk_probe()
1502 reg = readl(&priv->cru->cru_mode_con); in rk3288_clk_probe()
1511 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3288_clk_probe()
1515 rkclk_init(priv->cru, priv->grf); in rk3288_clk_probe()
1517 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3288_clk_probe()
1570 { .compatible = "rockchip,rk3288-cru" },
1607 printf("%s failed to get cru device\n", __func__); in soc_clk_dump()