Lines Matching +full:clk +full:- +full:div
4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
11 #include <dt-structs.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <dm/device-internal.h>
23 #include <dm/uclass-internal.h>
108 /* CLKSEL1: pd bus clk pll sel: codec or general */
114 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
118 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
122 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
135 * peripheral bus pclk div:
146 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
151 * peripheral bus aclk div:
210 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
236 const struct pll_div *div) in rkclk_set_pll() argument
239 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
241 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
242 uint output_hz = vco_hz / div->no; in rkclk_set_pll()
245 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
248 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
250 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, in rkclk_set_pll()
251 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
252 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
255 if (div->nb) in rkclk_set_pll()
256 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, div->nb - 1); in rkclk_set_pll()
258 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
263 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
275 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
282 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
289 con = readl(&pll->con0); in rkclk_pll_get_rate()
292 con = readl(&pll->con1); in rkclk_pll_get_rate()
328 return -EINVAL; in rkclk_configure_ddr()
331 /* pll enter slow-mode */ in rkclk_configure_ddr()
332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
338 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) in rkclk_configure_ddr()
341 /* PLL enter normal-mode */ in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
355 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config() argument
368 return -EINVAL; in pll_para_config()
379 div->nr = best_div->nr; in pll_para_config()
380 div->nf = best_div->nf; in pll_para_config()
381 div->no = best_div->no; in pll_para_config()
382 div->nb = best_div->nb; in pll_para_config()
397 return -1; in pll_para_config()
400 div->no = no; in pll_para_config()
413 diff_khz = vco_khz - nf * fref_khz; in pll_para_config()
416 diff_khz = fref_khz - diff_khz; in pll_para_config()
423 div->nr = nr; in pll_para_config()
424 div->nf = nf; in pll_para_config()
430 return -EINVAL; in pll_para_config()
444 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { in rockchip_mac_set_clk()
448 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk()
450 u8 div; in rockchip_mac_set_clk() local
461 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
462 if (div <= 0x1f) in rockchip_mac_set_clk()
463 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
464 div << MAC_DIV_CON_SHIFT); in rockchip_mac_set_clk()
466 debug("Unsupported div for gmac:%d\n", div); in rockchip_mac_set_clk()
468 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
485 /* vop dclk source clk: cpll,dclk_div: 1 */ in rockchip_vop_set_clk()
488 ret = (readl(&cru->cru_clksel_con[27]) & DCLK_VOP0_PLL_MASK) >> in rockchip_vop_set_clk()
495 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
501 if (readl(&grf->soc_status[1]) & in rockchip_vop_set_clk()
507 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
519 rk_clrsetreg(&cru->cru_clksel_con[27], in rockchip_vop_set_clk()
521 ((lcdc_div - 1) << DCLK_VOP0_DIV_SHIFT) | in rockchip_vop_set_clk()
525 ret = (readl(&cru->cru_clksel_con[29]) & DCLK_VOP1_PLL_MASK) >> in rockchip_vop_set_clk()
532 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
538 if (readl(&grf->soc_status[1]) & in rockchip_vop_set_clk()
544 rk_clrsetreg(&cru->cru_mode_con, CPLL_MODE_MASK, in rockchip_vop_set_clk()
557 rk_clrsetreg(&cru->cru_clksel_con[29], in rockchip_vop_set_clk()
559 ((lcdc_div - 1) << DCLK_VOP1_DIV_SHIFT) | in rockchip_vop_set_clk()
564 rk_clrsetreg(&cru->cru_clksel_con[31], in rockchip_vop_set_clk()
567 (lcdc_div - 1) << ACLK_VIO0_DIV_SHIFT); in rockchip_vop_set_clk()
571 rk_clrsetreg(&cru->cru_clksel_con[31], in rockchip_vop_set_clk()
574 (lcdc_div - 1) << ACLK_VIO1_DIV_SHIFT); in rockchip_vop_set_clk()
577 rk_clrsetreg(&cru->cru_clksel_con[28], in rockchip_vop_set_clk()
579 (lcdc_div - 1) << HCLK_VIO_DIV_SHIFT); in rockchip_vop_set_clk()
593 /* pll enter slow-mode */ in rkclk_init()
594 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
604 while ((readl(&grf->soc_status[1]) & in rkclk_init()
613 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; in rkclk_init()
615 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; in rkclk_init()
619 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; in rkclk_init()
623 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
635 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; in rkclk_init()
646 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
654 rk_clrsetreg(&cru->cru_clksel_con[39], in rkclk_init()
658 rk_clrsetreg(&cru->cru_clksel_con[42], in rkclk_init()
666 /* PLL enter normal-mode */ in rkclk_init()
667 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
675 /* pll enter slow-mode */ in rk3288_clk_configure_cpu()
676 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
682 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) in rk3288_clk_configure_cpu()
688 * core clock select apll, apll clk = 1800MHz in rk3288_clk_configure_cpu()
689 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz in rk3288_clk_configure_cpu()
691 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3288_clk_configure_cpu()
702 rk_clrsetreg(&cru->cru_clksel_con[37], in rk3288_clk_configure_cpu()
709 /* PLL enter normal-mode */ in rk3288_clk_configure_cpu()
710 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, in rk3288_clk_configure_cpu()
718 uint div, mux; in rockchip_mmc_get_clk() local
725 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
727 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
731 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
733 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rockchip_mmc_get_clk()
737 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
739 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; in rockchip_mmc_get_clk()
742 return -EINVAL; in rockchip_mmc_get_clk()
746 return DIV_TO_RATE(src_rate, div) / 2; in rockchip_mmc_get_clk()
756 /* mmc clock default div 2 internal, need provide double in cru */ in rockchip_mmc_set_clk()
773 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
776 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rockchip_mmc_set_clk()
780 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
783 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rockchip_mmc_set_clk()
787 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
790 (src_clk_div - 1) << SDIO0_DIV_SHIFT); in rockchip_mmc_set_clk()
793 return -EINVAL; in rockchip_mmc_set_clk()
802 uint div, mux; in rockchip_spi_get_clk() local
807 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
809 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; in rockchip_spi_get_clk()
812 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
814 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; in rockchip_spi_get_clk()
817 con = readl(&cru->cru_clksel_con[39]); in rockchip_spi_get_clk()
819 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; in rockchip_spi_get_clk()
822 return -EINVAL; in rockchip_spi_get_clk()
826 return DIV_TO_RATE(gclk_rate, div); in rockchip_spi_get_clk()
835 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; in rockchip_spi_set_clk()
839 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
845 rk_clrsetreg(&cru->cru_clksel_con[25], in rockchip_spi_set_clk()
851 rk_clrsetreg(&cru->cru_clksel_con[39], in rockchip_spi_set_clk()
857 return -EINVAL; in rockchip_spi_set_clk()
865 uint div, mux; in rockchip_aclk_peri_get_clk() local
869 con = readl(&cru->cru_clksel_con[10]); in rockchip_aclk_peri_get_clk()
871 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; in rockchip_aclk_peri_get_clk()
876 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_peri_get_clk()
883 uint div, mux; in rockchip_aclk_cpu_get_clk() local
887 con = readl(&cru->cru_clksel_con[1]); in rockchip_aclk_cpu_get_clk()
889 div = (con & PD_BUS_ACLK_DIV0_MASK) >> PD_BUS_ACLK_DIV0_SHIFT; in rockchip_aclk_cpu_get_clk()
894 parent_rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
896 div = (con & PD_BUS_ACLK_DIV1_MASK) >> PD_BUS_ACLK_DIV1_SHIFT; in rockchip_aclk_cpu_get_clk()
897 rate = DIV_TO_RATE(parent_rate, div); in rockchip_aclk_cpu_get_clk()
904 uint div; in rockchip_pclk_peri_get_clk() local
909 con = readl(&cru->cru_clksel_con[10]); in rockchip_pclk_peri_get_clk()
910 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT; in rockchip_pclk_peri_get_clk()
911 rate = parent_rate / (1 << div); in rockchip_pclk_peri_get_clk()
918 uint div; in rockchip_pclk_cpu_get_clk() local
923 con = readl(&cru->cru_clksel_con[1]); in rockchip_pclk_cpu_get_clk()
924 div = (con & PD_BUS_PCLK_DIV_MASK) >> PD_BUS_PCLK_DIV_SHIFT; in rockchip_pclk_cpu_get_clk()
925 rate = DIV_TO_RATE(parent_rate, div); in rockchip_pclk_cpu_get_clk()
942 return -EINVAL; in rockchip_i2c_get_clk()
948 u32 div, val; in rockchip_saradc_get_clk() local
950 val = readl(&cru->cru_clksel_con[24]); in rockchip_saradc_get_clk()
951 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, in rockchip_saradc_get_clk()
954 return DIV_TO_RATE(OSC_HZ, div); in rockchip_saradc_get_clk()
961 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
964 rk_clrsetreg(&cru->cru_clksel_con[24], in rockchip_saradc_set_clk()
973 u32 div, val; in rockchip_tsadc_get_clk() local
975 val = readl(&cru->cru_clksel_con[2]); in rockchip_tsadc_get_clk()
976 div = bitfield_extract(val, CLK_TSADC_DIV_CON_SHIFT, in rockchip_tsadc_get_clk()
979 return DIV_TO_RATE(32768, div); in rockchip_tsadc_get_clk()
986 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_tsadc_set_clk()
989 rk_clrsetreg(&cru->cru_clksel_con[2], in rockchip_tsadc_set_clk()
1000 u32 div, val; in rockchip_crypto_get_clk() local
1002 val = readl(&cru->cru_clksel_con[26]); in rockchip_crypto_get_clk()
1003 div = (val & CLK_CRYPTO_DIV_CON_MASK) >> CLK_CRYPTO_DIV_CON_SHIFT; in rockchip_crypto_get_clk()
1005 return DIV_TO_RATE(rockchip_aclk_cpu_get_clk(cru), div); in rockchip_crypto_get_clk()
1014 src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1; in rockchip_crypto_set_clk()
1017 rk_clrsetreg(&cru->cru_clksel_con[26], in rockchip_crypto_set_clk()
1026 u32 div, con, parent; in rk3288_alive_get_clk() local
1028 con = readl(&cru->cru_clksel_con[33]); in rk3288_alive_get_clk()
1029 div = (con & PCLK_ALIVE_DIV_CON_MASK) >> in rk3288_alive_get_clk()
1032 return DIV_TO_RATE(parent, div); in rk3288_alive_get_clk()
1039 val = readl(&cru->cru_misc_con); in rockchip_test_get_clk()
1049 return -ENOENT; in rockchip_test_get_clk()
1068 return -EINVAL; in rockchip_test_set_clk()
1070 rk_clrsetreg(&cru->cru_misc_con, in rockchip_test_set_clk()
1078 static ulong rk3288_clk_get_rate(struct clk *clk) in rk3288_clk_get_rate() argument
1080 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_clk_get_rate()
1083 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_get_rate()
1084 switch (clk->id) { in rk3288_clk_get_rate()
1086 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); in rk3288_clk_get_rate()
1096 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1101 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); in rk3288_clk_get_rate()
1109 new_rate = rockchip_i2c_get_clk(priv->cru, clk->id); in rk3288_clk_get_rate()
1115 new_rate = rockchip_saradc_get_clk(priv->cru); in rk3288_clk_get_rate()
1118 new_rate = rockchip_tsadc_get_clk(priv->cru); in rk3288_clk_get_rate()
1121 new_rate = rockchip_aclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
1124 new_rate = rockchip_aclk_peri_get_clk(priv->cru); in rk3288_clk_get_rate()
1127 new_rate = rockchip_pclk_cpu_get_clk(priv->cru); in rk3288_clk_get_rate()
1130 new_rate = rockchip_pclk_peri_get_clk(priv->cru); in rk3288_clk_get_rate()
1134 new_rate = rockchip_crypto_get_clk(priv->cru); in rk3288_clk_get_rate()
1137 new_rate = rk3288_alive_get_clk(priv->cru, gclk_rate); in rk3288_clk_get_rate()
1141 new_rate = rockchip_test_get_clk(priv->cru, clk->id); in rk3288_clk_get_rate()
1145 return -ENOENT; in rk3288_clk_get_rate()
1151 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) in rk3288_clk_set_rate() argument
1153 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_clk_set_rate()
1154 struct rk3288_cru *cru = priv->cru; in rk3288_clk_set_rate()
1157 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); in rk3288_clk_set_rate()
1158 switch (clk->id) { in rk3288_clk_set_rate()
1162 return -EINVAL; in rk3288_clk_set_rate()
1163 rk3288_clk_configure_cpu(priv->cru, priv->grf); in rk3288_clk_set_rate()
1167 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); in rk3288_clk_set_rate()
1175 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
1180 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); in rk3288_clk_set_rate()
1184 new_rate = rockchip_mac_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1190 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); in rk3288_clk_set_rate()
1194 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); in rk3288_clk_set_rate()
1197 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1199 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1204 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); in rk3288_clk_set_rate()
1207 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
1209 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
1213 new_rate = rockchip_crypto_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1217 new_rate = rockchip_test_set_clk(priv->cru, clk->id, rate); in rk3288_clk_set_rate()
1221 new_rate = rockchip_saradc_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1224 new_rate = rockchip_tsadc_set_clk(priv->cru, rate); in rk3288_clk_set_rate()
1238 return -ENOENT; in rk3288_clk_set_rate()
1251 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1256 int rockchip_mmc_get_phase(struct clk *clk) in rockchip_mmc_get_phase() argument
1258 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_get_phase()
1259 struct rk3288_cru *cru = priv->cru; in rockchip_mmc_get_phase()
1264 rate = rk3288_clk_get_rate(clk); in rockchip_mmc_get_phase()
1269 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_get_phase()
1270 raw_value = readl(&cru->cru_emmc_con[1]); in rockchip_mmc_get_phase()
1272 raw_value = readl(&cru->cru_sdmmc_con[1]); in rockchip_mmc_get_phase()
1289 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) in rockchip_mmc_set_phase() argument
1291 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_set_phase()
1292 struct rk3288_cru *cru = priv->cru; in rockchip_mmc_set_phase()
1297 rate = rk3288_clk_get_rate(clk); in rockchip_mmc_set_phase()
1307 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
1320 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_set_phase()
1321 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); in rockchip_mmc_set_phase()
1323 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); in rockchip_mmc_set_phase()
1326 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); in rockchip_mmc_set_phase()
1331 static int rk3288_clk_get_phase(struct clk *clk) in rk3288_clk_get_phase() argument
1335 switch (clk->id) { in rk3288_clk_get_phase()
1338 ret = rockchip_mmc_get_phase(clk); in rk3288_clk_get_phase()
1341 return -ENOENT; in rk3288_clk_get_phase()
1347 static int rk3288_clk_set_phase(struct clk *clk, int degrees) in rk3288_clk_set_phase() argument
1351 switch (clk->id) { in rk3288_clk_set_phase()
1354 ret = rockchip_mmc_set_phase(clk, degrees); in rk3288_clk_set_phase()
1357 return -ENOENT; in rk3288_clk_set_phase()
1363 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) in rk3288_gmac_set_parent() argument
1365 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_gmac_set_parent()
1366 struct rk3288_cru *cru = priv->cru; in rk3288_gmac_set_parent()
1371 * If the requested parent is in the same clock-controller and in rk3288_gmac_set_parent()
1375 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { in rk3288_gmac_set_parent()
1377 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); in rk3288_gmac_set_parent()
1382 * Otherwise, we need to check the clock-output-names of the in rk3288_gmac_set_parent()
1385 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk3288_gmac_set_parent()
1386 parent->id, &clock_output_name); in rk3288_gmac_set_parent()
1388 return -ENODATA; in rk3288_gmac_set_parent()
1393 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, in rk3288_gmac_set_parent()
1398 return -EINVAL; in rk3288_gmac_set_parent()
1401 static int __maybe_unused rk3288_vop_set_parent(struct clk *clk, in rk3288_vop_set_parent() argument
1402 struct clk *parent) in rk3288_vop_set_parent()
1404 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); in rk3288_vop_set_parent()
1405 struct rk3288_cru *cru = priv->cru; in rk3288_vop_set_parent()
1408 switch (parent->id) { in rk3288_vop_set_parent()
1423 switch (clk->id) { in rk3288_vop_set_parent()
1425 rk_clrsetreg(&cru->cru_clksel_con[27], in rk3288_vop_set_parent()
1429 rk_clrsetreg(&cru->cru_clksel_con[29], in rk3288_vop_set_parent()
1433 return -EINVAL; in rk3288_vop_set_parent()
1439 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) in rk3288_clk_set_parent() argument
1441 switch (clk->id) { in rk3288_clk_set_parent()
1443 return rk3288_gmac_set_parent(clk, parent); in rk3288_clk_set_parent()
1446 return rk3288_vop_set_parent(clk, parent); in rk3288_clk_set_parent()
1451 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk3288_clk_set_parent()
1452 return -ENOENT; in rk3288_clk_set_parent()
1470 priv->cru = dev_read_addr_ptr(dev); in rk3288_clk_ofdata_to_platdata()
1482 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3288_clk_probe()
1483 if (IS_ERR(priv->grf)) in rk3288_clk_probe()
1484 return PTR_ERR(priv->grf); in rk3288_clk_probe()
1489 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); in rk3288_clk_probe()
1493 if (!(gd->flags & GD_FLG_RELOC)) { in rk3288_clk_probe()
1497 * Init clocks in U-Boot proper if the NPLL is runnning. This in rk3288_clk_probe()
1499 * we need to redo it. U-Boot's SPL does not set this clock. in rk3288_clk_probe()
1502 reg = readl(&priv->cru->cru_mode_con); in rk3288_clk_probe()
1509 priv->sync_kernel = false; in rk3288_clk_probe()
1510 if (!priv->armclk_enter_hz) in rk3288_clk_probe()
1511 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, in rk3288_clk_probe()
1515 rkclk_init(priv->cru, priv->grf); in rk3288_clk_probe()
1516 if (!priv->armclk_init_hz) in rk3288_clk_probe()
1517 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, in rk3288_clk_probe()
1520 if (!priv->armclk_init_hz) in rk3288_clk_probe()
1521 priv->armclk_init_hz = priv->armclk_enter_hz; in rk3288_clk_probe()
1528 priv->sync_kernel = true; in rk3288_clk_probe()
1547 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, in rk3288_clk_bind()
1549 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, in rk3288_clk_bind()
1551 sys_child->priv = priv; in rk3288_clk_bind()
1560 sf_priv->sf_reset_offset = offsetof(struct rk3288_cru, in rk3288_clk_bind()
1562 sf_priv->sf_reset_num = 12; in rk3288_clk_bind()
1563 sf_child->priv = sf_priv; in rk3288_clk_bind()
1570 { .compatible = "rockchip,rk3288-cru" },
1588 * soc_clk_dump() - Print clock frequencies
1591 * Implementation for the clk dump command.
1598 struct clk clk; in soc_clk_dump() local
1612 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1613 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1614 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1615 priv->armclk_init_hz / 1000, in soc_clk_dump()
1616 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1617 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1620 if (clk_dump->name) { in soc_clk_dump()
1621 clk.id = clk_dump->id; in soc_clk_dump()
1622 if (clk_dump->is_cru) in soc_clk_dump()
1623 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1627 rate = clk_get_rate(&clk); in soc_clk_dump()
1628 clk_free(&clk); in soc_clk_dump()
1631 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1634 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1638 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1641 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()