Lines Matching refs:gpll_hz
175 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz; in rk322x_mmc_get_clk()
198 pll_rate = priv->gpll_hz; in rk322x_mac_set_clk()
225 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rk322x_mmc_set_clk()
279 parent = priv->gpll_hz; in rk322x_bus_get_clk()
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
357 parent = priv->gpll_hz; in rk322x_peri_get_clk()
388 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_peri_set_clk()
428 parent = priv->gpll_hz; in rk322x_spi_get_clk()
438 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_spi_set_clk()
457 parent = priv->gpll_hz; in rk322x_vop_get_clk()
469 parent = priv->gpll_hz; in rk322x_vop_get_clk()
495 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_vop_set_clk()
512 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_vop_set_clk()
538 parent = priv->gpll_hz; in rk322x_crypto_get_clk()
553 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_crypto_set_clk()
656 priv->gpll_hz = rate; in rk322x_clk_set_rate()
961 priv->gpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
994 priv->gpll_hz = GPLL_HZ; in rkclk_init()