Lines Matching +full:clk +full:- +full:div
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
17 #include <dt-bindings/clock/rk3228-cru.h>
22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
94 struct rk322x_cru *cru = priv->cru; in rk322x_armclk_set_clk()
101 return -EINVAL; in rk322x_armclk_set_clk()
110 priv->cru, APLL); in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
114 return -EINVAL; in rk322x_armclk_set_clk()
115 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
119 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
121 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk322x_armclk_set_clk()
122 rate->pclk_div << CORE_PERI_DIV_SHIFT); in rk322x_armclk_set_clk()
124 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
126 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk322x_armclk_set_clk()
127 rate->pclk_div << CORE_PERI_DIV_SHIFT); in rk322x_armclk_set_clk()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
133 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
134 return -EINVAL; in rk322x_armclk_set_clk()
137 return rockchip_pll_get_rate(&rk322x_pll_clks[APLL], priv->cru, APLL); in rk322x_armclk_set_clk()
143 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_get_clk()
145 uint div, mux; in rk322x_mmc_get_clk() local
152 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
154 con = readl(&cru->cru_clksel_con[12]); in rk322x_mmc_get_clk()
155 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rk322x_mmc_get_clk()
160 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
162 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rk322x_mmc_get_clk()
166 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
168 con = readl(&cru->cru_clksel_con[12]); in rk322x_mmc_get_clk()
169 div = (con & SDIO_DIV_MASK) >> SDIO_DIV_SHIFT; in rk322x_mmc_get_clk()
172 return -EINVAL; in rk322x_mmc_get_clk()
175 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz; in rk322x_mmc_get_clk()
176 return DIV_TO_RATE(src_rate, div) / 2; in rk322x_mmc_get_clk()
182 struct rk322x_cru *cru = priv->cru; in rk322x_mac_set_clk()
189 if (readl(&cru->cru_clksel_con[5]) & BIT(5)) { in rk322x_mac_set_clk()
193 u32 con = readl(&cru->cru_clksel_con[5]); in rk322x_mac_set_clk()
195 u8 div; in rk322x_mac_set_clk() local
198 pll_rate = priv->gpll_hz; in rk322x_mac_set_clk()
201 return -EPERM; in rk322x_mac_set_clk()
203 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
204 if (div <= 0x1f) in rk322x_mac_set_clk()
205 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, in rk322x_mac_set_clk()
206 div << CLK_MAC_DIV_SHIFT); in rk322x_mac_set_clk()
208 debug("Unsupported div for gmac:%d\n", div); in rk322x_mac_set_clk()
210 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
220 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_set_clk()
224 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rk322x_mmc_set_clk()
225 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rk322x_mmc_set_clk()
229 assert(src_clk_div - 1 < 128); in rk322x_mmc_set_clk()
239 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
242 rk_clrsetreg(&cru->cru_clksel_con[12], in rk322x_mmc_set_clk()
244 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk322x_mmc_set_clk()
249 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
252 (src_clk_div - 1) << MMC0_DIV_SHIFT); in rk322x_mmc_set_clk()
256 rk_clrsetreg(&cru->cru_clksel_con[11], in rk322x_mmc_set_clk()
259 rk_clrsetreg(&cru->cru_clksel_con[12], in rk322x_mmc_set_clk()
261 (src_clk_div - 1) << SDIO_DIV_SHIFT); in rk322x_mmc_set_clk()
264 return -EINVAL; in rk322x_mmc_set_clk()
272 struct rk322x_cru *cru = priv->cru; in rk322x_bus_get_clk()
273 u32 div, con, parent; in rk322x_bus_get_clk() local
277 con = readl(&cru->cru_clksel_con[0]); in rk322x_bus_get_clk()
278 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; in rk322x_bus_get_clk()
279 parent = priv->gpll_hz; in rk322x_bus_get_clk()
282 con = readl(&cru->cru_clksel_con[1]); in rk322x_bus_get_clk()
283 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; in rk322x_bus_get_clk()
292 con = readl(&cru->cru_clksel_con[1]); in rk322x_bus_get_clk()
293 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; in rk322x_bus_get_clk()
297 return -ENOENT; in rk322x_bus_get_clk()
300 return DIV_TO_RATE(parent, div); in rk322x_bus_get_clk()
306 struct rk322x_cru *cru = priv->cru; in rk322x_bus_set_clk()
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
316 assert(src_clk_div - 1 < 32); in rk322x_bus_set_clk()
317 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_bus_set_clk()
320 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); in rk322x_bus_set_clk()
326 assert(src_clk_div - 1 < 4); in rk322x_bus_set_clk()
327 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_bus_set_clk()
329 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); in rk322x_bus_set_clk()
335 assert(src_clk_div - 1 < 8); in rk322x_bus_set_clk()
336 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_bus_set_clk()
338 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); in rk322x_bus_set_clk()
342 return -EINVAL; in rk322x_bus_set_clk()
350 struct rk322x_cru *cru = priv->cru; in rk322x_peri_get_clk()
351 u32 div, con, parent; in rk322x_peri_get_clk() local
355 con = readl(&cru->cru_clksel_con[10]); in rk322x_peri_get_clk()
356 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; in rk322x_peri_get_clk()
357 parent = priv->gpll_hz; in rk322x_peri_get_clk()
360 con = readl(&cru->cru_clksel_con[10]); in rk322x_peri_get_clk()
361 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; in rk322x_peri_get_clk()
365 con = readl(&cru->cru_clksel_con[10]); in rk322x_peri_get_clk()
366 div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT; in rk322x_peri_get_clk()
370 return -ENOENT; in rk322x_peri_get_clk()
373 return DIV_TO_RATE(parent, div); in rk322x_peri_get_clk()
379 struct rk322x_cru *cru = priv->cru; in rk322x_peri_set_clk()
388 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_peri_set_clk()
389 assert(src_clk_div - 1 < 32); in rk322x_peri_set_clk()
390 rk_clrsetreg(&cru->cru_clksel_con[10], in rk322x_peri_set_clk()
393 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in rk322x_peri_set_clk()
399 assert(src_clk_div - 1 < 4); in rk322x_peri_set_clk()
400 rk_clrsetreg(&cru->cru_clksel_con[10], in rk322x_peri_set_clk()
402 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); in rk322x_peri_set_clk()
408 assert(src_clk_div - 1 < 8); in rk322x_peri_set_clk()
409 rk_clrsetreg(&cru->cru_clksel_con[10], in rk322x_peri_set_clk()
411 (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT); in rk322x_peri_set_clk()
415 return -EINVAL; in rk322x_peri_set_clk()
423 struct rk322x_cru *cru = priv->cru; in rk322x_spi_get_clk()
424 u32 div, con, parent; in rk322x_spi_get_clk() local
426 con = readl(&cru->cru_clksel_con[25]); in rk322x_spi_get_clk()
427 div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT; in rk322x_spi_get_clk()
428 parent = priv->gpll_hz; in rk322x_spi_get_clk()
430 return DIV_TO_RATE(parent, div); in rk322x_spi_get_clk()
435 struct rk322x_cru *cru = priv->cru; in rk322x_spi_set_clk()
436 int div; in rk322x_spi_set_clk() local
438 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_spi_set_clk()
439 assert(div - 1 < 128); in rk322x_spi_set_clk()
440 rk_clrsetreg(&cru->cru_clksel_con[25], in rk322x_spi_set_clk()
443 (div - 1) << SPI_DIV_SHIFT); in rk322x_spi_set_clk()
450 struct rk322x_cru *cru = priv->cru; in rk322x_vop_get_clk()
451 u32 div, con, sel, parent; in rk322x_vop_get_clk() local
455 con = readl(&cru->cru_clksel_con[33]); in rk322x_vop_get_clk()
456 div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT; in rk322x_vop_get_clk()
457 parent = priv->gpll_hz; in rk322x_vop_get_clk()
460 con = readl(&cru->cru_clksel_con[27]); in rk322x_vop_get_clk()
463 sel = readl(&cru->cru_clksel_con[27]); in rk322x_vop_get_clk()
467 parent = priv->cpll_hz; in rk322x_vop_get_clk()
469 parent = priv->gpll_hz; in rk322x_vop_get_clk()
471 con = readl(&cru->cru_clksel_con[27]); in rk322x_vop_get_clk()
472 div = (con & DCLK_LCDC_DIV_CON_MASK) >> in rk322x_vop_get_clk()
475 parent = priv->cpll_hz; in rk322x_vop_get_clk()
476 div = 1; in rk322x_vop_get_clk()
480 return -ENOENT; in rk322x_vop_get_clk()
483 return DIV_TO_RATE(parent, div); in rk322x_vop_get_clk()
489 struct rk322x_cru *cru = priv->cru; in rk322x_vop_set_clk()
495 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_vop_set_clk()
496 assert(src_clk_div - 1 < 32); in rk322x_vop_set_clk()
497 rk_clrsetreg(&cru->cru_clksel_con[33], in rk322x_vop_set_clk()
500 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); in rk322x_vop_set_clk()
503 con = readl(&cru->cru_clksel_con[27]); in rk322x_vop_set_clk()
506 parent = readl(&cru->cru_clksel_con[27]); in rk322x_vop_set_clk()
510 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk322x_vop_set_clk()
512 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_vop_set_clk()
514 assert(src_clk_div - 1 < 256); in rk322x_vop_set_clk()
515 rk_clrsetreg(&cru->cru_clksel_con[27], in rk322x_vop_set_clk()
517 (src_clk_div - 1) << in rk322x_vop_set_clk()
523 return -EINVAL; in rk322x_vop_set_clk()
531 struct rk322x_cru *cru = priv->cru; in rk322x_crypto_get_clk()
532 u32 div, con, parent; in rk322x_crypto_get_clk() local
536 con = readl(&cru->cru_clksel_con[24]); in rk322x_crypto_get_clk()
537 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in rk322x_crypto_get_clk()
538 parent = priv->gpll_hz; in rk322x_crypto_get_clk()
541 return -ENOENT; in rk322x_crypto_get_clk()
544 return DIV_TO_RATE(parent, div); in rk322x_crypto_get_clk()
550 struct rk322x_cru *cru = priv->cru; in rk322x_crypto_set_clk()
553 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_crypto_set_clk()
554 assert(src_clk_div - 1 <= 31); in rk322x_crypto_set_clk()
562 rk_clrsetreg(&cru->cru_clksel_con[24], in rk322x_crypto_set_clk()
565 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk322x_crypto_set_clk()
569 return -EINVAL; in rk322x_crypto_set_clk()
576 static ulong rk322x_clk_get_rate(struct clk *clk) in rk322x_clk_get_rate() argument
578 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_clk_get_rate()
581 switch (clk->id) { in rk322x_clk_get_rate()
586 rate = rockchip_pll_get_rate(&rk322x_pll_clks[clk->id - 1], in rk322x_clk_get_rate()
587 priv->cru, clk->id - 1); in rk322x_clk_get_rate()
591 priv->cru, APLL); in rk322x_clk_get_rate()
601 rate = rk322x_mmc_get_clk(priv, clk->id); in rk322x_clk_get_rate()
614 rate = rk322x_bus_get_clk(priv, clk->id); in rk322x_clk_get_rate()
619 rate = rk322x_peri_get_clk(priv, clk->id); in rk322x_clk_get_rate()
624 rate = rk322x_vop_get_clk(priv, clk->id); in rk322x_clk_get_rate()
627 rate = rk322x_crypto_get_clk(priv, clk->id); in rk322x_clk_get_rate()
631 return -ENOENT; in rk322x_clk_get_rate()
637 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) in rk322x_clk_set_rate() argument
639 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_clk_set_rate()
642 switch (clk->id) { in rk322x_clk_set_rate()
645 ret = rockchip_pll_set_rate(&rk322x_pll_clks[clk->id - 1], in rk322x_clk_set_rate()
646 priv->cru, clk->id - 1, rate); in rk322x_clk_set_rate()
650 priv->cru, CPLL, rate); in rk322x_clk_set_rate()
651 priv->cpll_hz = rate; in rk322x_clk_set_rate()
655 priv->cru, GPLL, rate); in rk322x_clk_set_rate()
656 priv->gpll_hz = rate; in rk322x_clk_set_rate()
659 if (priv->armclk_hz) in rk322x_clk_set_rate()
661 priv->armclk_hz = rate; in rk322x_clk_set_rate()
671 ret = rk322x_mmc_set_clk(priv, clk->id, rate); in rk322x_clk_set_rate()
675 priv->cru, DPLL, rate); in rk322x_clk_set_rate()
683 ret = rk322x_bus_set_clk(priv, clk->id, rate); in rk322x_clk_set_rate()
688 ret = rk322x_peri_set_clk(priv, clk->id, rate); in rk322x_clk_set_rate()
697 ret = rk322x_vop_set_clk(priv, clk->id, rate); in rk322x_clk_set_rate()
700 ret = rk322x_crypto_set_clk(priv, clk->id, rate); in rk322x_clk_set_rate()
704 return -ENOENT; in rk322x_clk_set_rate()
711 static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent) in rk322x_gmac_set_parent() argument
713 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_gmac_set_parent()
714 struct rk322x_cru *cru = priv->cru; in rk322x_gmac_set_parent()
717 * If the requested parent is in the same clock-controller and the id in rk322x_gmac_set_parent()
720 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) { in rk322x_gmac_set_parent()
722 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0); in rk322x_gmac_set_parent()
727 * If the requested parent is in the same clock-controller and the id in rk322x_gmac_set_parent()
730 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) { in rk322x_gmac_set_parent()
732 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5)); in rk322x_gmac_set_parent()
736 return -EINVAL; in rk322x_gmac_set_parent()
739 static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent) in rk322x_gmac_extclk_set_parent() argument
741 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_gmac_extclk_set_parent()
743 struct rk322x_cru *cru = priv->cru; in rk322x_gmac_extclk_set_parent()
746 ret = dev_read_string_index(parent->dev, "clock-output-names", in rk322x_gmac_extclk_set_parent()
747 parent->id, &clock_output_name); in rk322x_gmac_extclk_set_parent()
749 return -ENODATA; in rk322x_gmac_extclk_set_parent()
753 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0); in rk322x_gmac_extclk_set_parent()
757 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10)); in rk322x_gmac_extclk_set_parent()
761 return -EINVAL; in rk322x_gmac_extclk_set_parent()
764 static int rk322x_lcdc_set_parent(struct clk *clk, struct clk *parent) in rk322x_lcdc_set_parent() argument
766 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_lcdc_set_parent()
768 if (parent->id == HDMIPHY) in rk322x_lcdc_set_parent()
769 rk_clrsetreg(&priv->cru->cru_clksel_con[27], in rk322x_lcdc_set_parent()
772 else if (parent->id == PLL_CPLL) in rk322x_lcdc_set_parent()
773 rk_clrsetreg(&priv->cru->cru_clksel_con[27], in rk322x_lcdc_set_parent()
779 rk_clrsetreg(&priv->cru->cru_clksel_con[27], in rk322x_lcdc_set_parent()
789 static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) in rk322x_clk_set_parent() argument
791 switch (clk->id) { in rk322x_clk_set_parent()
794 return rk322x_gmac_set_parent(clk, parent); in rk322x_clk_set_parent()
796 return rk322x_gmac_extclk_set_parent(clk, parent); in rk322x_clk_set_parent()
798 return rk322x_lcdc_set_parent(clk, parent); in rk322x_clk_set_parent()
802 debug("%s: unsupported clk %ld\n", __func__, clk->id); in rk322x_clk_set_parent()
803 return -ENOENT; in rk322x_clk_set_parent()
813 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
818 int rk322x_mmc_get_phase(struct clk *clk) in rk322x_mmc_get_phase() argument
820 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_mmc_get_phase()
821 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_get_phase()
826 rate = rk322x_clk_get_rate(clk); in rk322x_mmc_get_phase()
831 if (clk->id == SCLK_EMMC_SAMPLE) in rk322x_mmc_get_phase()
832 raw_value = readl(&cru->cru_emmc_con[1]); in rk322x_mmc_get_phase()
833 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk322x_mmc_get_phase()
834 raw_value = readl(&cru->cru_sdmmc_con[1]); in rk322x_mmc_get_phase()
836 raw_value = readl(&cru->cru_sdio_con[1]); in rk322x_mmc_get_phase()
854 int rk322x_mmc_set_phase(struct clk *clk, u32 degrees) in rk322x_mmc_set_phase() argument
856 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); in rk322x_mmc_set_phase()
857 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_set_phase()
862 rate = rk322x_clk_get_rate(clk); in rk322x_mmc_set_phase()
872 * don't overflow 32-bit / 64-bit numbers. in rk322x_mmc_set_phase()
886 if (clk->id == SCLK_EMMC_SAMPLE) in rk322x_mmc_set_phase()
887 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); in rk322x_mmc_set_phase()
888 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk322x_mmc_set_phase()
889 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); in rk322x_mmc_set_phase()
891 writel(raw_value | 0xffff0000, &cru->cru_sdio_con[1]); in rk322x_mmc_set_phase()
894 degrees, delay_num, raw_value, rk322x_mmc_get_phase(clk)); in rk322x_mmc_set_phase()
899 static int rk322x_clk_get_phase(struct clk *clk) in rk322x_clk_get_phase() argument
903 debug("%s %ld\n", __func__, clk->id); in rk322x_clk_get_phase()
904 switch (clk->id) { in rk322x_clk_get_phase()
908 ret = rk322x_mmc_get_phase(clk); in rk322x_clk_get_phase()
911 return -ENOENT; in rk322x_clk_get_phase()
917 static int rk322x_clk_set_phase(struct clk *clk, int degrees) in rk322x_clk_set_phase() argument
921 debug("%s %ld\n", __func__, clk->id); in rk322x_clk_set_phase()
922 switch (clk->id) { in rk322x_clk_set_phase()
926 ret = rk322x_mmc_set_phase(clk, degrees); in rk322x_clk_set_phase()
929 return -ENOENT; in rk322x_clk_set_phase()
947 priv->cru = dev_read_addr_ptr(dev); in rk322x_clk_ofdata_to_platdata()
955 struct rk322x_cru *cru = priv->cru; in rkclk_init()
958 priv->cru, APLL) != APLL_HZ) in rkclk_init()
961 priv->gpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[GPLL], in rkclk_init()
962 priv->cru, GPLL); in rkclk_init()
963 priv->cpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
964 priv->cru, CPLL); in rkclk_init()
966 /* before set pll set child div first */ in rkclk_init()
972 rk_clrsetreg(&cru->cru_clksel_con[2], (0x1 << 14) | in rkclk_init()
974 rk_clrsetreg(&cru->cru_clksel_con[23], (0x1f << 0) | (0x1f << 8), in rkclk_init()
976 rk_clrsetreg(&cru->cru_clksel_con[33], in rkclk_init()
980 rk_clrsetreg(&cru->cru_clksel_con[22], 0x1f << 0, 5 << 0); in rkclk_init()
981 rk_clrsetreg(&cru->cru_clksel_con[24], 0x1f << 0, 0xb << 0); in rkclk_init()
982 rk_clrsetreg(&cru->cru_clksel_con[28], (0x1f << 8) | (0x1f << 0), in rkclk_init()
984 rk_clrsetreg(&cru->cru_clksel_con[31], (0x1f << 8) | (0x1f << 0), in rkclk_init()
986 rk_clrsetreg(&cru->cru_clksel_con[32], 0x1f << 0, 5 << 0); in rkclk_init()
987 rk_clrsetreg(&cru->cru_clksel_con[33], (0x1f << 8) | (0x1f << 0), in rkclk_init()
989 rk_clrsetreg(&cru->cru_clksel_con[34], (0x1f << 8) | (0x1f << 0), in rkclk_init()
993 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
994 priv->gpll_hz = GPLL_HZ; in rkclk_init()
997 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
998 priv->cpll_hz = CPLL_HZ; in rkclk_init()
1009 rk_clrsetreg(&cru->cru_misc_con, (0x1 << 13) | in rkclk_init()
1020 priv->sync_kernel = false; in rk322x_clk_probe()
1021 if (!priv->armclk_enter_hz) in rk322x_clk_probe()
1022 priv->armclk_enter_hz = in rk322x_clk_probe()
1024 priv->cru, APLL); in rk322x_clk_probe()
1026 if (!priv->armclk_init_hz) in rk322x_clk_probe()
1027 priv->armclk_init_hz = in rk322x_clk_probe()
1029 priv->cru, APLL); in rk322x_clk_probe()
1034 priv->sync_kernel = true; in rk322x_clk_probe()
1053 priv->glb_srst_fst_value = offsetof(struct rk322x_cru, in rk322x_clk_bind()
1055 priv->glb_srst_snd_value = offsetof(struct rk322x_cru, in rk322x_clk_bind()
1057 sys_child->priv = priv; in rk322x_clk_bind()
1066 sf_priv->sf_reset_offset = offsetof(struct rk322x_cru, in rk322x_clk_bind()
1068 sf_priv->sf_reset_num = 9; in rk322x_clk_bind()
1069 sf_child->priv = sf_priv; in rk322x_clk_bind()
1076 { .compatible = "rockchip,rk3228-cru" },
1093 * soc_clk_dump() - Print clock frequencies
1096 * Implementation for the clk dump command.
1103 struct clk clk; in soc_clk_dump() local
1117 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1118 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1119 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1120 priv->armclk_init_hz / 1000, in soc_clk_dump()
1121 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1122 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1125 if (clk_dump->name) { in soc_clk_dump()
1126 clk.id = clk_dump->id; in soc_clk_dump()
1127 if (clk_dump->is_cru) in soc_clk_dump()
1128 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1132 rate = clk_get_rate(&clk); in soc_clk_dump()
1133 clk_free(&clk); in soc_clk_dump()
1136 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1139 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1143 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1146 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()