58 	u32 nf;  member
94 	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
111 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;  in rkclk_set_pll()
115 	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);  in rkclk_set_pll()
126 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);  in rkclk_set_pll()
129 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);  in rkclk_set_pll()
143 		{.nf = 25, .nr = 2, .no = 1},  in rkclk_configure_ddr()
144 		{.nf = 400, .nr = 9, .no = 2},  in rkclk_configure_ddr()
145 		{.nf = 500, .nr = 9, .no = 2},  in rkclk_configure_ddr()
146 		{.nf = 100, .nr = 3, .no = 1},  in rkclk_configure_ddr()
189 		{.nf = 50, .nr = 1, .no = 2},  in rkclk_configure_cpu()
190 		{.nf = 67, .nr = 1, .no = 1},  in rkclk_configure_cpu()
248 	uint32_t nr, no, nf;  in rkclk_pll_get_rate()  local
269 		nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;  in rkclk_pll_get_rate()
271 		return (24 * nf / (nr * no)) * 1000000;  in rkclk_pll_get_rate()