Lines Matching refs:gpll_hz
173 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : priv->gpll_hz; in rockchip_mmc_get_clk()
185 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rockchip_mmc_set_clk()
232 parent = priv->gpll_hz; in rk3128_peri_get_clk()
266 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_peri_set_clk()
313 parent = priv->gpll_hz; in rk3128_bus_get_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_bus_set_clk()
381 parent = priv->gpll_hz; in rk3128_spi_get_clk()
391 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_spi_set_clk()
607 priv->gpll_hz = rate; in rk3128_clk_set_rate()
814 priv->gpll_hz = rockchip_pll_get_rate(&rk3128_pll_clks[GPLL], in rkclk_init()
820 priv->gpll_hz = GPLL_HZ; in rkclk_init()