Lines Matching full:cru
18 #include <dt-bindings/clock/rk3128-cru.h>
93 struct rk3128_cru *cru = priv->cru; in rk3128_armclk_set_clk() local
109 priv->cru, APLL); in rk3128_armclk_set_clk()
112 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
114 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
118 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
123 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
127 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
132 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
142 struct rk3128_cru *cru = priv->cru; in rockchip_mmc_get_clk() local
151 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
158 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
165 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
180 struct rk3128_cru *cru = priv->cru; in rockchip_mmc_set_clk() local
184 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rockchip_mmc_set_clk()
197 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
204 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
211 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
225 struct rk3128_cru *cru = priv->cru; in rk3128_peri_get_clk() local
230 con = readl(&cru->cru_clksel_con[10]); in rk3128_peri_get_clk()
241 con = readl(&cru->cru_clksel_con[10]); in rk3128_peri_get_clk()
246 con = readl(&cru->cru_clksel_con[10]); in rk3128_peri_get_clk()
261 struct rk3128_cru *cru = priv->cru; in rk3128_peri_set_clk() local
268 rk_clrsetreg(&cru->cru_clksel_con[10], in rk3128_peri_set_clk()
283 rk_clrsetreg(&cru->cru_clksel_con[10], in rk3128_peri_set_clk()
292 rk_clrsetreg(&cru->cru_clksel_con[10], in rk3128_peri_set_clk()
306 struct rk3128_cru *cru = priv->cru; in rk3128_bus_get_clk() local
311 con = readl(&cru->cru_clksel_con[0]); in rk3128_bus_get_clk()
316 con = readl(&cru->cru_clksel_con[1]); in rk3128_bus_get_clk()
321 con = readl(&cru->cru_clksel_con[1]); in rk3128_bus_get_clk()
336 struct rk3128_cru *cru = priv->cru; in rk3128_bus_set_clk() local
343 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_bus_set_clk()
353 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_bus_set_clk()
362 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_bus_set_clk()
376 struct rk3128_cru *cru = priv->cru; in rk3128_spi_get_clk() local
379 con = readl(&cru->cru_clksel_con[25]); in rk3128_spi_get_clk()
388 struct rk3128_cru *cru = priv->cru; in rk3128_spi_set_clk() local
393 rk_clrsetreg(&cru->cru_clksel_con[25], in rk3128_spi_set_clk()
403 struct rk3128_cru *cru = priv->cru; in rk3128_saradc_get_clk() local
406 val = readl(&cru->cru_clksel_con[24]); in rk3128_saradc_get_clk()
415 struct rk3128_cru *cru = priv->cru; in rk3128_saradc_set_clk() local
421 rk_clrsetreg(&cru->cru_clksel_con[24], in rk3128_saradc_set_clk()
433 struct rk3128_cru *cru = priv->cru; in rk3128_vop_set_clk() local
442 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3128_vop_set_clk()
448 rk_clrsetreg(&cru->cru_clksel_con[31], in rk3128_vop_set_clk()
456 priv->cru, CPLL, src_clk_div * hz); in rk3128_vop_set_clk()
457 rk_clrsetreg(&cru->cru_clksel_con[27], in rk3128_vop_set_clk()
472 struct rk3128_cru *cru = priv->cru; in rk3128_vop_get_rate() local
478 con = readl(&cru->cru_clksel_con[31]); in rk3128_vop_get_rate()
483 con = readl(&cru->cru_clksel_con[31]); in rk3128_vop_get_rate()
488 con = readl(&cru->cru_clksel_con[27]); in rk3128_vop_get_rate()
491 priv->cru, CPLL); in rk3128_vop_get_rate()
501 struct rk3128_cru *cru = priv->cru; in rk3128_crypto_get_rate() local
504 val = readl(&cru->cru_clksel_con[24]); in rk3128_crypto_get_rate()
513 struct rk3128_cru *cru = priv->cru; in rk3128_crypto_set_rate() local
521 rk_clrsetreg(&cru->cru_clksel_con[24], in rk3128_crypto_set_rate()
540 priv->cru, clk->id - 1); in rk3128_clk_get_rate()
544 priv->cru, APLL); in rk3128_clk_get_rate()
603 priv->cru, clk->id - 1, rate); in rk3128_clk_set_rate()
606 priv->cru, GPLL, rate); in rk3128_clk_set_rate()
678 struct rk3128_cru *cru = priv->cru; in rk3128_mmc_get_phase() local
689 raw_value = readl(&cru->cru_emmc_con[1]); in rk3128_mmc_get_phase()
691 raw_value = readl(&cru->cru_sdmmc_con[1]); in rk3128_mmc_get_phase()
693 raw_value = readl(&cru->cru_sdio_con[1]); in rk3128_mmc_get_phase()
714 struct rk3128_cru *cru = priv->cru; in rk3128_mmc_set_phase() local
744 writel(raw_value | 0xffff0000, &cru->cru_emmc_con[1]); in rk3128_mmc_set_phase()
746 writel(raw_value | 0xffff0000, &cru->cru_sdmmc_con[1]); in rk3128_mmc_set_phase()
748 writel(raw_value | 0xffff0000, &cru->cru_sdio_con[1]); in rk3128_mmc_set_phase()
803 priv->cru = dev_read_addr_ptr(dev); in rk3128_clk_ofdata_to_platdata()
811 priv->cru, APLL) != APLL_HZ) in rkclk_init()
815 priv->cru, GPLL); in rkclk_init()
819 priv->cru, GPLL, GPLL_HZ); in rkclk_init()
821 rk_clrsetreg(&priv->cru->cru_clksel_con[2], in rkclk_init()
825 rk_clrsetreg(&priv->cru->cru_clksel_con[11], in rkclk_init()
838 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
849 priv->cru, APLL); in rk3128_clk_probe()
854 priv->cru, APLL); in rk3128_clk_probe()
896 { .compatible = "rockchip,rk3128-cru" },
897 { .compatible = "rockchip,rk3126-cru" },
933 printf("%s failed to get cru device\n", __func__); in soc_clk_dump()