91 static ulong rk3128_armclk_set_clk(struct rk3128_clk_priv *priv, ulong hz)  in rk3128_armclk_set_clk()  argument
97 	rate = rockchip_get_cpu_settings(rk3128_cpu_rates, hz);  in rk3128_armclk_set_clk()
106 	 * core hz : apll = 1:1  in rk3128_armclk_set_clk()
110 	if (old_rate > hz) {  in rk3128_armclk_set_clk()
112 					  priv->cru, APLL, hz))  in rk3128_armclk_set_clk()
122 	} else if (old_rate < hz) {  in rk3128_armclk_set_clk()
132 					  priv->cru, APLL, hz))  in rk3128_armclk_set_clk()
187 	if (src_clk_div > 128) {  in rockchip_mmc_set_clk()
259 				 ulong clk_id, uint hz)  in rk3128_peri_set_clk()  argument
266 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3128_peri_set_clk()
281 					   hz);  in rk3128_peri_set_clk()
290 					   hz);  in rk3128_peri_set_clk()
334 				ulong clk_id, uint hz)  in rk3128_bus_set_clk()  argument
341 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3128_bus_set_clk()
351 					   hz);  in rk3128_bus_set_clk()
360 					   hz);  in rk3128_bus_set_clk()
386 static ulong rk3128_spi_set_clk(struct rk3128_clk_priv *priv, ulong hz)  in rk3128_spi_set_clk()  argument
391 	div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3128_spi_set_clk()
392 	assert(div - 1 < 128);  in rk3128_spi_set_clk()
413 static ulong rk3128_saradc_set_clk(struct rk3128_clk_priv *priv, uint hz)  in rk3128_saradc_set_clk()  argument
418 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3128_saradc_set_clk()
419 	assert(src_clk_div < 128);  in rk3128_saradc_set_clk()
431 				ulong clk_id, uint hz)  in rk3128_vop_set_clk()  argument
436 	src_clk_div = GPLL_HZ / hz;  in rk3128_vop_set_clk()
454 		src_clk_div = DIV_ROUND_UP(RK3128_LCDC_PLL_LIMIT, hz);  in rk3128_vop_set_clk()
456 				      priv->cru, CPLL, src_clk_div * hz);  in rk3128_vop_set_clk()
467 	return hz;  in rk3128_vop_set_clk()
511 				    uint hz)  in rk3128_crypto_set_rate()  argument
518 	src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1;  in rk3128_crypto_set_rate()