57 	u32 nf;  member
96 	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
113 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;  in rkclk_set_pll()
117 	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);  in rkclk_set_pll()
128 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);  in rkclk_set_pll()
131 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);  in rkclk_set_pll()
145 		{.nf = 25, .nr = 2, .no = 1},  in rkclk_configure_ddr()
146 		{.nf = 400, .nr = 9, .no = 2},  in rkclk_configure_ddr()
147 		{.nf = 500, .nr = 9, .no = 2},  in rkclk_configure_ddr()
148 		{.nf = 100, .nr = 3, .no = 1},  in rkclk_configure_ddr()
191 		{.nf = 50, .nr = 1, .no = 2},  in rkclk_configure_cpu()
192 		{.nf = 59, .nr = 1, .no = 1},  in rkclk_configure_cpu()
250 	uint32_t nr, no, nf;  in rkclk_pll_get_rate()  local
271 		nf = ((con >> CLKF_SHIFT) & (CLKF_MASK >> CLKF_SHIFT)) + 1;  in rkclk_pll_get_rate()
273 		return (24 * nf / (nr * no)) * 1000000;  in rkclk_pll_get_rate()