49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\  argument
51 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
53 	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
55 			 #hz "Hz cannot be hit with PLL "\
73 		 vco=%u Hz, output=%u Hz\n",  in rkclk_set_pll()
122 	 * core hz : apll = 1:1  in rkclk_init()
281 	if (src_clk_div > 128) {  in rockchip_mmc_set_clk()
283 		assert(src_clk_div - 1 < 128);  in rockchip_mmc_set_clk()
323 				 ulong hz)  in rk3036_spi_set_clk()  argument
327 	div = DIV_ROUND_UP(clk_general_rate, hz);  in rk3036_spi_set_clk()
328 	assert(div - 1 < 128);  in rk3036_spi_set_clk()
427 				 uint hz)  in rk3036_peri_set_clk()  argument
434 		src_clk_div = DIV_ROUND_UP(clk_general_rate, hz);  in rk3036_peri_set_clk()
445 							       hz);  in rk3036_peri_set_clk()