Lines Matching refs:gpll_hz
130 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_i2c_get_clk()
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
218 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk1808_mmc_get_clk()
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
276 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_sfc_get_clk()
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
344 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_pwm_get_clk()
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
432 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_spi_get_clk()
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
482 parent = priv->gpll_hz; in rk1808_vop_get_clk()
507 parent = priv->gpll_hz; in rk1808_vop_get_clk()
522 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
567 } else if (!(priv->gpll_hz % hz)) { in rk1808_vop_set_clk()
569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
664 parent = priv->gpll_hz; in rk1808_crypto_get_clk()
669 parent = priv->gpll_hz; in rk1808_crypto_get_clk()
684 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_crypto_set_clk()
722 parent = priv->gpll_hz; in rk1808_bus_get_clk()
727 parent = priv->gpll_hz; in rk1808_bus_get_clk()
733 parent = priv->gpll_hz; in rk1808_bus_get_clk()
754 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
762 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
770 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
795 parent = priv->gpll_hz; in rk1808_peri_get_clk()
801 parent = priv->gpll_hz; in rk1808_peri_get_clk()
816 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_peri_set_clk()
1018 priv->gpll_hz = rate; in rk1808_clk_set_rate()
1310 priv->gpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()