Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
12 #include <clk.h>
18 #include <dt-bindings/clock/rk1808-cru.h>
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
97 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_get_clk()
98 u32 div, con; in rk1808_i2c_get_clk() local
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
103 div = (con & CLK_I2C0_DIV_CON_MASK) >> CLK_I2C0_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
107 div = (con & CLK_I2C1_DIV_CON_MASK) >> CLK_I2C1_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
110 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
111 div = (con & CLK_I2C2_DIV_CON_MASK) >> CLK_I2C2_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
114 con = readl(&cru->clksel_con[60]); in rk1808_i2c_get_clk()
115 div = (con & CLK_I2C3_DIV_CON_MASK) >> CLK_I2C3_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
118 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
119 div = (con & CLK_I2C4_DIV_CON_MASK) >> CLK_I2C4_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
122 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
123 div = (con & CLK_I2C5_DIV_CON_MASK) >> CLK_I2C5_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
127 return -EINVAL; in rk1808_i2c_get_clk()
130 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_i2c_get_clk()
136 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_set_clk()
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
140 assert(src_clk_div - 1 < 127); in rk1808_i2c_set_clk()
144 rk_clrsetreg(&cru->pmu_clksel_con[7], in rk1808_i2c_set_clk()
146 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
150 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
152 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
156 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
158 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
162 rk_clrsetreg(&cru->clksel_con[60], in rk1808_i2c_set_clk()
164 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
168 rk_clrsetreg(&cru->clksel_con[71], in rk1808_i2c_set_clk()
170 (src_clk_div - 1) << CLK_I2C4_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
174 rk_clrsetreg(&cru->clksel_con[71], in rk1808_i2c_set_clk()
176 (src_clk_div - 1) << CLK_I2C5_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
181 return -EINVAL; in rk1808_i2c_set_clk()
190 struct rk1808_cru *cru = priv->cru; in rk1808_mmc_get_clk()
191 u32 div, con, con_id; in rk1808_mmc_get_clk() local
208 return -EINVAL; in rk1808_mmc_get_clk()
211 con = readl(&cru->clksel_con[con_id]); in rk1808_mmc_get_clk()
212 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rk1808_mmc_get_clk()
216 return DIV_TO_RATE(OSC_HZ, div) / 2; in rk1808_mmc_get_clk()
218 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rk1808_mmc_get_clk()
224 struct rk1808_cru *cru = priv->cru; in rk1808_mmc_set_clk()
242 return -EINVAL; in rk1808_mmc_set_clk()
246 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rk1808_mmc_set_clk()
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
252 rk_clrsetreg(&cru->clksel_con[con_id], in rk1808_mmc_set_clk()
255 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
257 rk_clrsetreg(&cru->clksel_con[con_id], in rk1808_mmc_set_clk()
260 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
262 rk_clrsetreg(&cru->clksel_con[con_id + 1], EMMC_CLK_SEL_MASK, in rk1808_mmc_set_clk()
270 struct rk1808_cru *cru = priv->cru; in rk1808_sfc_get_clk()
271 u32 div, con; in rk1808_sfc_get_clk() local
273 con = readl(&cru->clksel_con[26]); in rk1808_sfc_get_clk()
274 div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT; in rk1808_sfc_get_clk()
276 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_sfc_get_clk()
282 struct rk1808_cru *cru = priv->cru; in rk1808_sfc_set_clk()
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
286 rk_clrsetreg(&cru->clksel_con[26], in rk1808_sfc_set_clk()
289 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); in rk1808_sfc_set_clk()
296 struct rk1808_cru *cru = priv->cru; in rk1808_saradc_get_clk()
297 u32 div, con; in rk1808_saradc_get_clk() local
299 con = readl(&cru->clksel_con[63]); in rk1808_saradc_get_clk()
300 div = con & CLK_SARADC_DIV_CON_MASK; in rk1808_saradc_get_clk()
302 return DIV_TO_RATE(OSC_HZ, div); in rk1808_saradc_get_clk()
307 struct rk1808_cru *cru = priv->cru; in rk1808_saradc_set_clk()
311 assert(src_clk_div - 1 < 2047); in rk1808_saradc_set_clk()
313 rk_clrsetreg(&cru->clksel_con[63], in rk1808_saradc_set_clk()
315 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_saradc_set_clk()
323 struct rk1808_cru *cru = priv->cru; in rk1808_pwm_get_clk()
324 u32 div, con; in rk1808_pwm_get_clk() local
328 con = readl(&cru->clksel_con[69]); in rk1808_pwm_get_clk()
329 div = (con & CLK_PWM0_DIV_CON_MASK) >> CLK_PWM0_DIV_CON_SHIFT; in rk1808_pwm_get_clk()
332 con = readl(&cru->clksel_con[69]); in rk1808_pwm_get_clk()
333 div = (con & CLK_PWM1_DIV_CON_MASK) >> CLK_PWM1_DIV_CON_SHIFT; in rk1808_pwm_get_clk()
336 con = readl(&cru->clksel_con[70]); in rk1808_pwm_get_clk()
337 div = (con & CLK_PWM2_DIV_CON_MASK) >> CLK_PWM2_DIV_CON_SHIFT; in rk1808_pwm_get_clk()
341 return -EINVAL; in rk1808_pwm_get_clk()
344 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_pwm_get_clk()
350 struct rk1808_cru *cru = priv->cru; in rk1808_pwm_set_clk()
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
354 assert(src_clk_div - 1 < 127); in rk1808_pwm_set_clk()
358 rk_clrsetreg(&cru->clksel_con[69], in rk1808_pwm_set_clk()
360 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
364 rk_clrsetreg(&cru->clksel_con[69], in rk1808_pwm_set_clk()
366 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
370 rk_clrsetreg(&cru->clksel_con[70], in rk1808_pwm_set_clk()
372 (src_clk_div - 1) << CLK_PWM2_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
377 return -EINVAL; in rk1808_pwm_set_clk()
385 struct rk1808_cru *cru = priv->cru; in rk1808_tsadc_get_clk()
386 u32 div, con; in rk1808_tsadc_get_clk() local
388 con = readl(&cru->clksel_con[62]); in rk1808_tsadc_get_clk()
389 div = con & CLK_SARADC_DIV_CON_MASK; in rk1808_tsadc_get_clk()
391 return DIV_TO_RATE(OSC_HZ, div); in rk1808_tsadc_get_clk()
396 struct rk1808_cru *cru = priv->cru; in rk1808_tsadc_set_clk()
400 assert(src_clk_div - 1 < 2047); in rk1808_tsadc_set_clk()
402 rk_clrsetreg(&cru->clksel_con[62], in rk1808_tsadc_set_clk()
404 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_tsadc_set_clk()
411 struct rk1808_cru *cru = priv->cru; in rk1808_spi_get_clk()
412 u32 div, con; in rk1808_spi_get_clk() local
416 con = readl(&cru->clksel_con[60]); in rk1808_spi_get_clk()
417 div = (con & CLK_SPI0_DIV_CON_MASK) >> CLK_SPI0_DIV_CON_SHIFT; in rk1808_spi_get_clk()
420 con = readl(&cru->clksel_con[61]); in rk1808_spi_get_clk()
421 div = (con & CLK_SPI1_DIV_CON_MASK) >> CLK_SPI1_DIV_CON_SHIFT; in rk1808_spi_get_clk()
424 con = readl(&cru->clksel_con[61]); in rk1808_spi_get_clk()
425 div = (con & CLK_SPI2_DIV_CON_MASK) >> CLK_SPI2_DIV_CON_SHIFT; in rk1808_spi_get_clk()
429 return -EINVAL; in rk1808_spi_get_clk()
432 return DIV_TO_RATE(priv->gpll_hz, div); in rk1808_spi_get_clk()
438 struct rk1808_cru *cru = priv->cru; in rk1808_spi_set_clk()
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
442 assert(src_clk_div - 1 < 127); in rk1808_spi_set_clk()
446 rk_clrsetreg(&cru->clksel_con[60], in rk1808_spi_set_clk()
448 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | in rk1808_spi_set_clk()
452 rk_clrsetreg(&cru->clksel_con[61], in rk1808_spi_set_clk()
454 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | in rk1808_spi_set_clk()
458 rk_clrsetreg(&cru->clksel_con[61], in rk1808_spi_set_clk()
460 (src_clk_div - 1) << CLK_SPI2_DIV_CON_SHIFT | in rk1808_spi_set_clk()
465 return -EINVAL; in rk1808_spi_set_clk()
474 struct rk1808_cru *cru = priv->cru; in rk1808_vop_get_clk()
475 u32 div, con, parent; in rk1808_vop_get_clk() local
480 con = readl(&cru->clksel_con[4]); in rk1808_vop_get_clk()
481 div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT; in rk1808_vop_get_clk()
482 parent = priv->gpll_hz; in rk1808_vop_get_clk()
487 con = readl(&cru->clksel_con[4]); in rk1808_vop_get_clk()
488 div = (con & HCLK_VOP_DIV_CON_MASK) >> HCLK_VOP_DIV_CON_SHIFT; in rk1808_vop_get_clk()
491 con = readl(&cru->clksel_con[5]); in rk1808_vop_get_clk()
492 div = con & DCLK_VOPRAW_DIV_CON_MASK; in rk1808_vop_get_clk()
494 priv->cru, NPLL); in rk1808_vop_get_clk()
497 con = readl(&cru->clksel_con[7]); in rk1808_vop_get_clk()
498 div = con & DCLK_VOPLITE_DIV_CON_MASK; in rk1808_vop_get_clk()
503 priv->cru, NPLL); in rk1808_vop_get_clk()
505 parent = priv->cpll_hz; in rk1808_vop_get_clk()
507 parent = priv->gpll_hz; in rk1808_vop_get_clk()
510 return -ENOENT; in rk1808_vop_get_clk()
513 return DIV_TO_RATE(parent, div); in rk1808_vop_get_clk()
519 struct rk1808_cru *cru = priv->cru; in rk1808_vop_set_clk()
522 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
523 assert(src_clk_div - 1 < 31); in rk1808_vop_set_clk()
528 rk_clrsetreg(&cru->clksel_con[4], in rk1808_vop_set_clk()
531 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
537 assert(src_clk_div - 1 < 15); in rk1808_vop_set_clk()
538 rk_clrsetreg(&cru->clksel_con[4], in rk1808_vop_set_clk()
540 (src_clk_div - 1) << HCLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
547 rk_clrsetreg(&cru->clksel_con[5], in rk1808_vop_set_clk()
555 ((src_clk_div - 1) << DCLK_VOPRAW_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
557 priv->cru, NPLL, src_clk_div * hz); in rk1808_vop_set_clk()
564 if (!(priv->cpll_hz % hz)) { in rk1808_vop_set_clk()
566 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk1808_vop_set_clk()
567 } else if (!(priv->gpll_hz % hz)) { in rk1808_vop_set_clk()
569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
575 priv->cru, NPLL, in rk1808_vop_set_clk()
578 rk_clrsetreg(&cru->clksel_con[7], in rk1808_vop_set_clk()
584 ((src_clk_div - 1) << DCLK_VOPLITE_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
588 return -EINVAL; in rk1808_vop_set_clk()
594 static ulong rk1808_mac_set_clk(struct clk *clk, uint hz) in rk1808_mac_set_clk() argument
596 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_mac_set_clk()
597 struct rk1808_cru *cru = priv->cru; in rk1808_mac_set_clk()
598 u32 con = readl(&cru->clksel_con[26]); in rk1808_mac_set_clk()
600 u8 div; in rk1808_mac_set_clk() local
604 priv->cru, NPLL); in rk1808_mac_set_clk()
607 priv->cru, PPLL); in rk1808_mac_set_clk()
610 priv->cru, CPLL); in rk1808_mac_set_clk()
616 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk1808_mac_set_clk()
617 assert(div < 32); in rk1808_mac_set_clk()
618 rk_clrsetreg(&cru->clksel_con[26], CLK_GMAC_DIV_MASK, in rk1808_mac_set_clk()
619 div << CLK_GMAC_DIV_SHIFT); in rk1808_mac_set_clk()
621 return DIV_TO_RATE(pll_rate, div); in rk1808_mac_set_clk()
624 static int rk1808_mac_set_speed_clk(struct clk *clk, ulong clk_id, uint hz) in rk1808_mac_set_speed_clk() argument
626 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_mac_set_speed_clk()
627 struct rk1808_cru *cru = priv->cru; in rk1808_mac_set_speed_clk()
638 rk_clrsetreg(&cru->clksel_con[27], RGMII_CLK_SEL_MASK, in rk1808_mac_set_speed_clk()
646 rk_clrsetreg(&cru->clksel_con[27], RMII_CLK_SEL_MASK, in rk1808_mac_set_speed_clk()
650 return -ENOENT; in rk1808_mac_set_speed_clk()
657 struct rk1808_cru *cru = priv->cru; in rk1808_crypto_get_clk()
658 u32 div, con, parent; in rk1808_crypto_get_clk() local
662 con = readl(&cru->clksel_con[29]); in rk1808_crypto_get_clk()
663 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in rk1808_crypto_get_clk()
664 parent = priv->gpll_hz; in rk1808_crypto_get_clk()
667 con = readl(&cru->clksel_con[29]); in rk1808_crypto_get_clk()
668 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; in rk1808_crypto_get_clk()
669 parent = priv->gpll_hz; in rk1808_crypto_get_clk()
672 return -ENOENT; in rk1808_crypto_get_clk()
675 return DIV_TO_RATE(parent, div); in rk1808_crypto_get_clk()
681 struct rk1808_cru *cru = priv->cru; in rk1808_crypto_set_clk()
684 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_crypto_set_clk()
685 assert(src_clk_div - 1 <= 31); in rk1808_crypto_set_clk()
693 rk_clrsetreg(&cru->clksel_con[29], in rk1808_crypto_set_clk()
696 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk1808_crypto_set_clk()
699 rk_clrsetreg(&cru->clksel_con[29], in rk1808_crypto_set_clk()
702 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in rk1808_crypto_set_clk()
706 return -EINVAL; in rk1808_crypto_set_clk()
715 struct rk1808_cru *cru = priv->cru; in rk1808_bus_get_clk()
716 u32 div, con, parent; in rk1808_bus_get_clk() local
720 con = readl(&cru->clksel_con[27]); in rk1808_bus_get_clk()
721 div = (con & HSCLK_BUS_DIV_CON_MASK) >> HSCLK_BUS_DIV_CON_SHIFT; in rk1808_bus_get_clk()
722 parent = priv->gpll_hz; in rk1808_bus_get_clk()
725 con = readl(&cru->clksel_con[28]); in rk1808_bus_get_clk()
726 div = (con & MSCLK_BUS_DIV_CON_MASK) >> MSCLK_BUS_DIV_CON_SHIFT; in rk1808_bus_get_clk()
727 parent = priv->gpll_hz; in rk1808_bus_get_clk()
731 con = readl(&cru->clksel_con[28]); in rk1808_bus_get_clk()
732 div = (con & LSCLK_BUS_DIV_CON_MASK) >> LSCLK_BUS_DIV_CON_SHIFT; in rk1808_bus_get_clk()
733 parent = priv->gpll_hz; in rk1808_bus_get_clk()
736 return -ENOENT; in rk1808_bus_get_clk()
739 return DIV_TO_RATE(parent, div); in rk1808_bus_get_clk()
745 struct rk1808_cru *cru = priv->cru; in rk1808_bus_set_clk()
754 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
755 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
756 rk_clrsetreg(&cru->clksel_con[27], in rk1808_bus_set_clk()
759 (src_clk_div - 1) << HSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
762 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
763 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
764 rk_clrsetreg(&cru->clksel_con[28], in rk1808_bus_set_clk()
767 (src_clk_div - 1) << MSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
770 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
771 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
772 rk_clrsetreg(&cru->clksel_con[28], in rk1808_bus_set_clk()
775 (src_clk_div - 1) << LSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
779 return -EINVAL; in rk1808_bus_set_clk()
787 struct rk1808_cru *cru = priv->cru; in rk1808_peri_get_clk()
788 u32 div, con, parent; in rk1808_peri_get_clk() local
792 con = readl(&cru->clksel_con[19]); in rk1808_peri_get_clk()
793 div = (con & MSCLK_PERI_DIV_CON_MASK) >> in rk1808_peri_get_clk()
795 parent = priv->gpll_hz; in rk1808_peri_get_clk()
798 con = readl(&cru->clksel_con[19]); in rk1808_peri_get_clk()
799 div = (con & LSCLK_PERI_DIV_CON_MASK) >> in rk1808_peri_get_clk()
801 parent = priv->gpll_hz; in rk1808_peri_get_clk()
804 return -ENOENT; in rk1808_peri_get_clk()
807 return DIV_TO_RATE(parent, div); in rk1808_peri_get_clk()
813 struct rk1808_cru *cru = priv->cru; in rk1808_peri_set_clk()
816 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_peri_set_clk()
817 assert(src_clk_div - 1 < 31); in rk1808_peri_set_clk()
825 rk_clrsetreg(&cru->clksel_con[19], in rk1808_peri_set_clk()
828 (src_clk_div - 1) << MSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
831 rk_clrsetreg(&cru->clksel_con[19], in rk1808_peri_set_clk()
834 (src_clk_div - 1) << LSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
838 return -EINVAL; in rk1808_peri_set_clk()
847 struct rk1808_cru *cru = priv->cru; in rk1808_pclk_pmu_set_clk()
851 assert(src_clk_div - 1 < 31); in rk1808_pclk_pmu_set_clk()
853 rk_clrsetreg(&cru->pmu_clksel_con[0], in rk1808_pclk_pmu_set_clk()
855 (src_clk_div - 1) << PCLK_PMU_DIV_CON_SHIFT); in rk1808_pclk_pmu_set_clk()
862 struct rk1808_cru *cru = priv->cru; in rk1808_armclk_set_clk()
869 return -EINVAL; in rk1808_armclk_set_clk()
878 priv->cru, APLL); in rk1808_armclk_set_clk()
881 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
882 return -EINVAL; in rk1808_armclk_set_clk()
883 rk_clrsetreg(&cru->clksel_con[0], in rk1808_armclk_set_clk()
886 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk1808_armclk_set_clk()
887 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk1808_armclk_set_clk()
891 rk_clrsetreg(&cru->clksel_con[0], in rk1808_armclk_set_clk()
894 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk1808_armclk_set_clk()
895 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk1808_armclk_set_clk()
899 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
900 return -EINVAL; in rk1808_armclk_set_clk()
903 return rockchip_pll_get_rate(&rk1808_pll_clks[APLL], priv->cru, APLL); in rk1808_armclk_set_clk()
906 static ulong rk1808_clk_get_rate(struct clk *clk) in rk1808_clk_get_rate() argument
908 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_clk_get_rate()
911 debug("%s %ld\n", __func__, clk->id); in rk1808_clk_get_rate()
912 switch (clk->id) { in rk1808_clk_get_rate()
919 rate = rockchip_pll_get_rate(&rk1808_pll_clks[clk->id - 1], in rk1808_clk_get_rate()
920 priv->cru, clk->id - 1); in rk1808_clk_get_rate()
924 priv->cru, APLL); in rk1808_clk_get_rate()
933 rate = rk1808_mmc_get_clk(priv, clk->id); in rk1808_clk_get_rate()
936 rate = rk1808_sfc_get_clk(priv, clk->id); in rk1808_clk_get_rate()
948 rate = rk1808_i2c_get_clk(priv, clk->id); in rk1808_clk_get_rate()
953 rate = rk1808_pwm_get_clk(priv, clk->id); in rk1808_clk_get_rate()
961 rate = rk1808_spi_get_clk(priv, clk->id); in rk1808_clk_get_rate()
967 rate = rk1808_vop_get_clk(priv, clk->id); in rk1808_clk_get_rate()
971 rate = rk1808_crypto_get_clk(priv, clk->id); in rk1808_clk_get_rate()
978 rate = rk1808_bus_get_clk(priv, clk->id); in rk1808_clk_get_rate()
982 rate = rk1808_peri_get_clk(priv, clk->id); in rk1808_clk_get_rate()
985 return -ENOENT; in rk1808_clk_get_rate()
991 static ulong rk1808_clk_set_rate(struct clk *clk, ulong rate) in rk1808_clk_set_rate() argument
993 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_clk_set_rate()
996 debug("%s %ld %ld\n", __func__, clk->id, rate); in rk1808_clk_set_rate()
997 switch (clk->id) { in rk1808_clk_set_rate()
1000 ret = rockchip_pll_set_rate(&rk1808_pll_clks[clk->id - 1], in rk1808_clk_set_rate()
1001 priv->cru, clk->id - 1, rate); in rk1808_clk_set_rate()
1004 ret = rk1808_pclk_pmu_set_clk(priv, clk->id, rate, PCLK_PMU_HZ); in rk1808_clk_set_rate()
1006 priv->cru, PPLL, rate); in rk1808_clk_set_rate()
1010 priv->cru, CPLL, rate); in rk1808_clk_set_rate()
1012 priv->cpll_hz = rate; in rk1808_clk_set_rate()
1016 priv->cru, GPLL, rate); in rk1808_clk_set_rate()
1018 priv->gpll_hz = rate; in rk1808_clk_set_rate()
1022 priv->cru, NPLL, rate); in rk1808_clk_set_rate()
1024 priv->npll_hz = rate; in rk1808_clk_set_rate()
1027 if (priv->armclk_hz) in rk1808_clk_set_rate()
1029 priv->armclk_hz = rate; in rk1808_clk_set_rate()
1037 ret = rk1808_mmc_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1040 ret = rk1808_sfc_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1052 ret = rk1808_i2c_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1057 ret = rk1808_pwm_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1065 ret = rk1808_spi_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1071 ret = rk1808_vop_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1075 ret = rk1808_mac_set_clk(clk, rate); in rk1808_clk_set_rate()
1079 ret = rk1808_mac_set_speed_clk(clk, clk->id, rate); in rk1808_clk_set_rate()
1083 ret = rk1808_crypto_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1089 ret = rk1808_bus_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1093 ret = rk1808_peri_set_clk(priv, clk->id, rate); in rk1808_clk_set_rate()
1098 return -ENOENT; in rk1808_clk_set_rate()
1111 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1116 int rk1808_mmc_get_phase(struct clk *clk) in rk1808_mmc_get_phase() argument
1118 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_mmc_get_phase()
1119 struct rk1808_cru *cru = priv->cru; in rk1808_mmc_get_phase()
1124 rate = rk1808_clk_get_rate(clk); in rk1808_mmc_get_phase()
1129 if (clk->id == SCLK_EMMC_SAMPLE) in rk1808_mmc_get_phase()
1130 raw_value = readl(&cru->emmc_con[1]); in rk1808_mmc_get_phase()
1131 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk1808_mmc_get_phase()
1132 raw_value = readl(&cru->sdmmc_con[1]); in rk1808_mmc_get_phase()
1134 raw_value = readl(&cru->sdio_con[1]); in rk1808_mmc_get_phase()
1152 int rk1808_mmc_set_phase(struct clk *clk, u32 degrees) in rk1808_mmc_set_phase() argument
1154 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_mmc_set_phase()
1155 struct rk1808_cru *cru = priv->cru; in rk1808_mmc_set_phase()
1160 rate = rk1808_clk_get_rate(clk); in rk1808_mmc_set_phase()
1170 * don't overflow 32-bit / 64-bit numbers. in rk1808_mmc_set_phase()
1184 if (clk->id == SCLK_EMMC_SAMPLE) in rk1808_mmc_set_phase()
1185 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rk1808_mmc_set_phase()
1186 else if (clk->id == SCLK_SDMMC_SAMPLE) in rk1808_mmc_set_phase()
1187 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk1808_mmc_set_phase()
1189 writel(raw_value | 0xffff0000, &cru->sdio_con[1]); in rk1808_mmc_set_phase()
1192 degrees, delay_num, raw_value, rk1808_mmc_get_phase(clk)); in rk1808_mmc_set_phase()
1197 static int rk1808_clk_get_phase(struct clk *clk) in rk1808_clk_get_phase() argument
1201 debug("%s %ld\n", __func__, clk->id); in rk1808_clk_get_phase()
1202 switch (clk->id) { in rk1808_clk_get_phase()
1206 ret = rk1808_mmc_get_phase(clk); in rk1808_clk_get_phase()
1209 return -ENOENT; in rk1808_clk_get_phase()
1215 static int rk1808_clk_set_phase(struct clk *clk, int degrees) in rk1808_clk_set_phase() argument
1219 debug("%s %ld\n", __func__, clk->id); in rk1808_clk_set_phase()
1220 switch (clk->id) { in rk1808_clk_set_phase()
1224 ret = rk1808_mmc_set_phase(clk, degrees); in rk1808_clk_set_phase()
1227 return -ENOENT; in rk1808_clk_set_phase()
1234 static int rk1808_gmac_set_parent(struct clk *clk, struct clk *parent) in rk1808_gmac_set_parent() argument
1236 struct rk1808_clk_priv *priv = dev_get_priv(clk->dev); in rk1808_gmac_set_parent()
1237 struct rk1808_cru *cru = priv->cru; in rk1808_gmac_set_parent()
1239 if (parent->id == SCLK_GMAC_SRC) { in rk1808_gmac_set_parent()
1241 rk_clrsetreg(&cru->clksel_con[27], RMII_EXTCLK_SEL_MASK, in rk1808_gmac_set_parent()
1245 rk_clrsetreg(&cru->clksel_con[27], RMII_EXTCLK_SEL_MASK, in rk1808_gmac_set_parent()
1251 static int rk1808_clk_set_parent(struct clk *clk, struct clk *parent) in rk1808_clk_set_parent() argument
1253 switch (clk->id) { in rk1808_clk_set_parent()
1255 return rk1808_gmac_set_parent(clk, parent); in rk1808_clk_set_parent()
1259 return -ENOENT; in rk1808_clk_set_parent()
1283 priv->sync_kernel = false; in rk1808_clk_probe()
1284 if (!priv->armclk_enter_hz) { in rk1808_clk_probe()
1285 priv->armclk_enter_hz = in rk1808_clk_probe()
1287 priv->cru, APLL); in rk1808_clk_probe()
1288 priv->armclk_init_hz = priv->armclk_enter_hz; in rk1808_clk_probe()
1291 priv->cru, APLL) != APLL_HZ) { in rk1808_clk_probe()
1295 priv->armclk_init_hz = APLL_HZ; in rk1808_clk_probe()
1299 * The eMMC clk is depended on gpll, and the eMMC is needed to in rk1808_clk_probe()
1304 priv->cru, GPLL, GPLL_HZ); in rk1808_clk_probe()
1308 priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_probe()
1309 priv->cru, CPLL); in rk1808_clk_probe()
1310 priv->gpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[GPLL], in rk1808_clk_probe()
1311 priv->cru, GPLL); in rk1808_clk_probe()
1312 priv->npll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_clk_probe()
1313 priv->cru, NPLL); in rk1808_clk_probe()
1323 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rk1808_clk_probe()
1328 priv->sync_kernel = true; in rk1808_clk_probe()
1345 priv->cru = dev_read_addr_ptr(dev); in rk1808_clk_ofdata_to_platdata()
1364 priv->glb_srst_fst_value = offsetof(struct rk1808_cru, in rk1808_clk_bind()
1366 priv->glb_srst_snd_value = offsetof(struct rk1808_cru, in rk1808_clk_bind()
1368 sys_child->priv = priv; in rk1808_clk_bind()
1377 sf_priv->sf_reset_offset = offsetof(struct rk1808_cru, in rk1808_clk_bind()
1379 sf_priv->sf_reset_num = 16; in rk1808_clk_bind()
1380 sf_child->priv = sf_priv; in rk1808_clk_bind()
1387 { .compatible = "rockchip,rk1808-cru" },
1404 * soc_clk_dump() - Print clock frequencies
1407 * Implementation for the clk dump command.
1414 struct clk clk; in soc_clk_dump() local
1428 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
1429 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1430 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1431 priv->armclk_init_hz / 1000, in soc_clk_dump()
1432 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1433 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1437 if (clk_dump->name) { in soc_clk_dump()
1438 clk.id = clk_dump->id; in soc_clk_dump()
1439 if (clk_dump->is_cru) in soc_clk_dump()
1440 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
1444 rate = clk_get_rate(&clk); in soc_clk_dump()
1445 clk_free(&clk); in soc_clk_dump()
1448 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1451 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1455 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1458 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()