Lines Matching +full:1 +full:hz
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
34 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
38 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
39 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
40 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
41 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
42 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
43 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
44 RK3036_PLL_RATE(200000000, 1, 200, 6, 4, 1, 0),
45 RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
73 RK1808_CPUCLK_RATE(1200000000, 1, 5),
74 RK1808_CPUCLK_RATE(1008000000, 1, 5),
75 RK1808_CPUCLK_RATE(816000000, 1, 3),
76 RK1808_CPUCLK_RATE(600000000, 1, 3),
134 ulong clk_id, uint hz) in rk1808_i2c_set_clk() argument
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
140 assert(src_clk_div - 1 < 127); in rk1808_i2c_set_clk()
146 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
152 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
158 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
164 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
170 (src_clk_div - 1) << CLK_I2C4_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
176 (src_clk_div - 1) << CLK_I2C5_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
255 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
260 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
262 rk_clrsetreg(&cru->clksel_con[con_id + 1], EMMC_CLK_SEL_MASK, in rk1808_mmc_set_clk()
289 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); in rk1808_sfc_set_clk()
305 static ulong rk1808_saradc_set_clk(struct rk1808_clk_priv *priv, uint hz) in rk1808_saradc_set_clk() argument
310 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_saradc_set_clk()
311 assert(src_clk_div - 1 < 2047); in rk1808_saradc_set_clk()
315 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_saradc_set_clk()
348 ulong clk_id, uint hz) in rk1808_pwm_set_clk() argument
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
354 assert(src_clk_div - 1 < 127); in rk1808_pwm_set_clk()
360 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
366 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
372 (src_clk_div - 1) << CLK_PWM2_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
394 static ulong rk1808_tsadc_set_clk(struct rk1808_clk_priv *priv, uint hz) in rk1808_tsadc_set_clk() argument
399 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_tsadc_set_clk()
400 assert(src_clk_div - 1 < 2047); in rk1808_tsadc_set_clk()
404 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_tsadc_set_clk()
436 ulong clk_id, uint hz) in rk1808_spi_set_clk() argument
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
442 assert(src_clk_div - 1 < 127); in rk1808_spi_set_clk()
448 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | in rk1808_spi_set_clk()
454 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | in rk1808_spi_set_clk()
460 (src_clk_div - 1) << CLK_SPI2_DIV_CON_SHIFT | in rk1808_spi_set_clk()
517 ulong clk_id, uint hz) in rk1808_vop_set_clk() argument
522 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
523 assert(src_clk_div - 1 < 31); in rk1808_vop_set_clk()
531 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
536 DIV_ROUND_UP(rk1808_vop_get_clk(priv, ACLK_VOPRAW), hz); in rk1808_vop_set_clk()
537 assert(src_clk_div - 1 < 15); in rk1808_vop_set_clk()
540 (src_clk_div - 1) << HCLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
546 src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ, hz); in rk1808_vop_set_clk()
555 ((src_clk_div - 1) << DCLK_VOPRAW_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
557 priv->cru, NPLL, src_clk_div * hz); in rk1808_vop_set_clk()
564 if (!(priv->cpll_hz % hz)) { in rk1808_vop_set_clk()
566 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk1808_vop_set_clk()
567 } else if (!(priv->gpll_hz % hz)) { in rk1808_vop_set_clk()
569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
573 hz); in rk1808_vop_set_clk()
576 src_clk_div * hz); in rk1808_vop_set_clk()
584 ((src_clk_div - 1) << DCLK_VOPLITE_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
594 static ulong rk1808_mac_set_clk(struct clk *clk, uint hz) in rk1808_mac_set_clk() argument
613 if (!hz) in rk1808_mac_set_clk()
614 hz = 50000000; in rk1808_mac_set_clk()
616 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk1808_mac_set_clk()
624 static int rk1808_mac_set_speed_clk(struct clk *clk, ulong clk_id, uint hz) in rk1808_mac_set_speed_clk() argument
632 if (hz == 125000000) in rk1808_mac_set_speed_clk()
634 else if (hz == 2500000) in rk1808_mac_set_speed_clk()
642 if (hz == 2500000) in rk1808_mac_set_speed_clk()
645 sel = 1; in rk1808_mac_set_speed_clk()
679 ulong hz) in rk1808_crypto_set_clk() argument
684 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_crypto_set_clk()
685 assert(src_clk_div - 1 <= 31); in rk1808_crypto_set_clk()
696 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk1808_crypto_set_clk()
702 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in rk1808_crypto_set_clk()
743 ulong clk_id, ulong hz) in rk1808_bus_set_clk() argument
754 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
755 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
759 (src_clk_div - 1) << HSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
762 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
763 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
767 (src_clk_div - 1) << MSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
770 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
771 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
775 (src_clk_div - 1) << LSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
811 ulong clk_id, ulong hz) in rk1808_peri_set_clk() argument
816 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_peri_set_clk()
817 assert(src_clk_div - 1 < 31); in rk1808_peri_set_clk()
828 (src_clk_div - 1) << MSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
834 (src_clk_div - 1) << LSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
845 ulong clk_id, ulong parent_hz, ulong hz) in rk1808_pclk_pmu_set_clk() argument
850 src_clk_div = DIV_ROUND_UP(parent_hz, hz); in rk1808_pclk_pmu_set_clk()
851 assert(src_clk_div - 1 < 31); in rk1808_pclk_pmu_set_clk()
855 (src_clk_div - 1) << PCLK_PMU_DIV_CON_SHIFT); in rk1808_pclk_pmu_set_clk()
860 static ulong rk1808_armclk_set_clk(struct rk1808_clk_priv *priv, ulong hz) in rk1808_armclk_set_clk() argument
866 rate = rockchip_get_cpu_settings(rk1808_cpu_rates, hz); in rk1808_armclk_set_clk()
875 * core hz : apll = 1:1 in rk1808_armclk_set_clk()
879 if (old_rate > hz) { in rk1808_armclk_set_clk()
881 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
890 } else if (old_rate < hz) { in rk1808_armclk_set_clk()
899 priv->cru, APLL, hz)) in rk1808_armclk_set_clk()
919 rate = rockchip_pll_get_rate(&rk1808_pll_clks[clk->id - 1], in rk1808_clk_get_rate()
920 priv->cru, clk->id - 1); in rk1808_clk_get_rate()
1000 ret = rockchip_pll_set_rate(&rk1808_pll_clks[clk->id - 1], in rk1808_clk_set_rate()
1001 priv->cru, clk->id - 1, rate); in rk1808_clk_set_rate()
1130 raw_value = readl(&cru->emmc_con[1]); in rk1808_mmc_get_phase()
1132 raw_value = readl(&cru->sdmmc_con[1]); in rk1808_mmc_get_phase()
1134 raw_value = readl(&cru->sdio_con[1]); in rk1808_mmc_get_phase()
1136 raw_value >>= 1; in rk1808_mmc_get_phase()
1183 raw_value <<= 1; in rk1808_mmc_set_phase()
1185 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rk1808_mmc_set_phase()
1187 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rk1808_mmc_set_phase()
1189 writel(raw_value | 0xffff0000, &cru->sdio_con[1]); in rk1808_mmc_set_phase()