241 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
249 	rk_clrsetreg(&pll->con0,  in rkclk_set_pll()
252 	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,  in rkclk_set_pll()
263 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
337 		rk_clrsetreg(&cru->clksel_con[49],  in px30_i2c_set_clk()
344 		rk_clrsetreg(&cru->clksel_con[49],  in px30_i2c_set_clk()
351 		rk_clrsetreg(&cru->clksel_con[50],  in px30_i2c_set_clk()
358 		rk_clrsetreg(&cru->clksel_con[50],  in px30_i2c_set_clk()
466 		rk_clrsetreg(&cru->clksel_con[30],  in px30_i2s_set_clk()
468 		rk_clrsetreg(&cru->clksel_con[30],  in px30_i2s_set_clk()
470 		rk_clrsetreg(&cru->clksel_con[30],  in px30_i2s_set_clk()
474 		rk_clrsetreg(&cru->clkgate_con[10],  in px30_i2s_set_clk()
505 		rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK,  in px30_i2s1_mclk_set_clk()
509 		rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK,  in px30_i2s1_mclk_set_clk()
513 	rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK,  in px30_i2s1_mclk_set_clk()
541 	rk_clrsetreg(&cru->clksel_con[15],  in px30_nandc_set_clk()
608 		rk_clrsetreg(&cru->clksel_con[con_id],  in px30_mmc_set_clk()
613 		rk_clrsetreg(&cru->clksel_con[con_id],  in px30_mmc_set_clk()
618 	rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK,  in px30_mmc_set_clk()
642 	rk_clrsetreg(&cru->clksel_con[22],  in px30_sfc_set_clk()
682 		rk_clrsetreg(&cru->clksel_con[52],  in px30_pwm_set_clk()
689 		rk_clrsetreg(&cru->clksel_con[52],  in px30_pwm_set_clk()
722 	rk_clrsetreg(&cru->clksel_con[55],  in px30_saradc_set_clk()
748 	rk_clrsetreg(&cru->clksel_con[54],  in px30_tsadc_set_clk()
787 		rk_clrsetreg(&cru->clksel_con[53],  in px30_spi_set_clk()
794 		rk_clrsetreg(&cru->clksel_con[53],  in px30_spi_set_clk()
848 		rk_clrsetreg(&cru->clksel_con[3],  in px30_vop_set_clk()
863 		rk_clrsetreg(&cru->clksel_con[5],  in px30_vop_set_clk()
886 		rk_clrsetreg(&cru->clksel_con[8],  in px30_vop_set_clk()
944 		rk_clrsetreg(&cru->clksel_con[23],  in px30_bus_set_clk()
952 		rk_clrsetreg(&cru->clksel_con[24],  in px30_bus_set_clk()
961 		rk_clrsetreg(&cru->clksel_con[24],  in px30_bus_set_clk()
1011 		rk_clrsetreg(&cru->clksel_con[14],  in px30_peri_set_clk()
1017 		rk_clrsetreg(&cru->clksel_con[14],  in px30_peri_set_clk()
1079 		rk_clrsetreg(&cru->clksel_con[56],  in px30_otp_set_clk()
1089 		rk_clrsetreg(&cru->clksel_con[56],  in px30_otp_set_clk()
1095 		rk_clrsetreg(&cru->clksel_con[56],  in px30_otp_set_clk()
1145 		rk_clrsetreg(&cru->clksel_con[25],  in px30_crypto_set_clk()
1151 		rk_clrsetreg(&cru->clksel_con[25],  in px30_crypto_set_clk()
1186 	rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK,  in px30_mac_set_clk()
1202 	rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK,  in px30_mac_set_speed_clk()
1268 		rk_clrsetreg(&cru->clksel_con[0],  in px30_armclk_set_clk()
1276 		rk_clrsetreg(&cru->clksel_con[0],  in px30_armclk_set_clk()
1609 		rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK,  in px30_gmac_set_parent()
1613 		rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK,  in px30_gmac_set_parent()
1755 	rk_clrsetreg(&pmucru->pmu_clksel_con[0],  in px30_pclk_pmu_set_pmuclk()