105 				   enum px30_pll_id pll_id);
215 			 enum px30_pll_id pll_id,  in rkclk_set_pll()  argument
241 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
242 		     PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]);  in rkclk_set_pll()
263 	rk_clrsetreg(mode, pll_mode_mask[pll_id],  in rkclk_set_pll()
264 		     PLLMUX_FROM_PLL << pll_mode_shift[pll_id]);  in rkclk_set_pll()
270 				   enum px30_pll_id pll_id)  in rkclk_pll_get_rate()  argument
276 	shift = pll_mode_shift[pll_id];  in rkclk_pll_get_rate()
277 	mask = pll_mode_mask[pll_id];  in rkclk_pll_get_rate()
1230 				   enum px30_pll_id pll_id)  in px30_clk_get_pll_rate()  argument
1234 	return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);  in px30_clk_get_pll_rate()
1238 				   enum px30_pll_id pll_id, ulong hz)  in px30_clk_set_pll_rate()  argument
1242 	if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz))  in px30_clk_set_pll_rate()
1244 	return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);  in px30_clk_set_pll_rate()