Lines Matching +full:clk +full:- +full:div
4 * SPDX-License-Identifier: GPL-2.0
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/px30-cru.h>
51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
149 diff_khz = vco_khz - fbdiv * fref_khz; in pll_clk_set_by_auto()
152 diff_khz = fref_khz - diff_khz; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
206 * FOUTVCO = Fractional PLL non-divided output frequency
224 return -EINVAL; in rkclk_set_pll()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
229 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
233 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
245 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
247 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
249 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
251 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); in rkclk_set_pll()
252 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
254 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
257 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
260 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) in rkclk_set_pll()
284 con = readl(&pll->con0); in rkclk_pll_get_rate()
287 con = readl(&pll->con1); in rkclk_pll_get_rate()
299 struct px30_cru *cru = priv->cru; in px30_i2c_get_clk()
300 u32 div, con; in px30_i2c_get_clk() local
304 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
305 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
308 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
309 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
312 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
313 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
316 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
317 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
321 return -EINVAL; in px30_i2c_get_clk()
324 return DIV_TO_RATE(priv->gpll_hz, div); in px30_i2c_get_clk()
329 struct px30_cru *cru = priv->cru; in px30_i2c_set_clk()
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
333 assert(src_clk_div - 1 <= 127); in px30_i2c_set_clk()
337 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
340 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in px30_i2c_set_clk()
344 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
347 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in px30_i2c_set_clk()
351 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
354 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in px30_i2c_set_clk()
358 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
361 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in px30_i2c_set_clk()
366 return -EINVAL; in px30_i2c_set_clk()
380 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
431 struct px30_cru *cru = priv->cru; in px30_i2s_get_clk()
435 con = readl(&cru->clksel_con[30]); in px30_i2s_get_clk()
436 fracdiv = readl(&cru->clksel_con[31]); in px30_i2s_get_clk()
437 gate = readl(&cru->clkgate_con[10]); in px30_i2s_get_clk()
447 return -EINVAL; in px30_i2s_get_clk()
457 struct px30_cru *cru = priv->cru; in px30_i2s_set_clk()
461 GENMASK(16 - 1, 0), in px30_i2s_set_clk()
462 GENMASK(16 - 1, 0), in px30_i2s_set_clk()
466 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
468 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
470 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
473 writel(val, &cru->clksel_con[31]); in px30_i2s_set_clk()
474 rk_clrsetreg(&cru->clkgate_con[10], in px30_i2s_set_clk()
480 return -EINVAL; in px30_i2s_set_clk()
488 struct px30_cru *cru = priv->cru; in px30_i2s1_mclk_get_clk()
491 con = readl(&cru->clksel_con[30]); in px30_i2s1_mclk_get_clk()
502 struct px30_cru *cru = priv->cru; in px30_i2s1_mclk_set_clk()
505 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, in px30_i2s1_mclk_set_clk()
509 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, in px30_i2s1_mclk_set_clk()
513 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK, in px30_i2s1_mclk_set_clk()
521 struct px30_cru *cru = priv->cru; in px30_nandc_get_clk()
522 u32 div, con; in px30_nandc_get_clk() local
524 con = readl(&cru->clksel_con[15]); in px30_nandc_get_clk()
525 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; in px30_nandc_get_clk()
527 return DIV_TO_RATE(priv->gpll_hz, div); in px30_nandc_get_clk()
533 struct px30_cru *cru = priv->cru; in px30_nandc_set_clk()
537 /* nandc clock defaulg div 2 internal, need provide double in cru */ in px30_nandc_set_clk()
538 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
539 assert(src_clk_div - 1 <= 31); in px30_nandc_set_clk()
541 rk_clrsetreg(&cru->clksel_con[15], in px30_nandc_set_clk()
546 (src_clk_div - 1) << NANDC_DIV_SHIFT); in px30_nandc_set_clk()
553 struct px30_cru *cru = priv->cru; in px30_mmc_get_clk()
554 u32 div, con, con_id; in px30_mmc_get_clk() local
567 return -EINVAL; in px30_mmc_get_clk()
570 con = readl(&cru->clksel_con[con_id]); in px30_mmc_get_clk()
571 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in px30_mmc_get_clk()
575 return DIV_TO_RATE(OSC_HZ, div) / 2; in px30_mmc_get_clk()
577 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in px30_mmc_get_clk()
584 struct px30_cru *cru = priv->cru; in px30_mmc_set_clk()
598 return -EINVAL; in px30_mmc_set_clk()
602 /* mmc clock defaulg div 2 internal, need provide double in cru */ in px30_mmc_set_clk()
603 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in px30_mmc_set_clk()
608 rk_clrsetreg(&cru->clksel_con[con_id], in px30_mmc_set_clk()
611 (src_clk_div - 1) << EMMC_DIV_SHIFT); in px30_mmc_set_clk()
613 rk_clrsetreg(&cru->clksel_con[con_id], in px30_mmc_set_clk()
616 (src_clk_div - 1) << EMMC_DIV_SHIFT); in px30_mmc_set_clk()
618 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, in px30_mmc_set_clk()
626 struct px30_cru *cru = priv->cru; in px30_sfc_get_clk()
627 u32 div, con; in px30_sfc_get_clk() local
629 con = readl(&cru->clksel_con[22]); in px30_sfc_get_clk()
630 div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT; in px30_sfc_get_clk()
632 return DIV_TO_RATE(priv->gpll_hz, div); in px30_sfc_get_clk()
638 struct px30_cru *cru = priv->cru; in px30_sfc_set_clk()
641 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_sfc_set_clk()
642 rk_clrsetreg(&cru->clksel_con[22], in px30_sfc_set_clk()
645 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); in px30_sfc_set_clk()
652 struct px30_cru *cru = priv->cru; in px30_pwm_get_clk()
653 u32 div, con; in px30_pwm_get_clk() local
657 con = readl(&cru->clksel_con[52]); in px30_pwm_get_clk()
658 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; in px30_pwm_get_clk()
661 con = readl(&cru->clksel_con[52]); in px30_pwm_get_clk()
662 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; in px30_pwm_get_clk()
666 return -EINVAL; in px30_pwm_get_clk()
669 return DIV_TO_RATE(priv->gpll_hz, div); in px30_pwm_get_clk()
674 struct px30_cru *cru = priv->cru; in px30_pwm_set_clk()
677 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
678 assert(src_clk_div - 1 <= 127); in px30_pwm_set_clk()
682 rk_clrsetreg(&cru->clksel_con[52], in px30_pwm_set_clk()
685 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | in px30_pwm_set_clk()
689 rk_clrsetreg(&cru->clksel_con[52], in px30_pwm_set_clk()
692 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | in px30_pwm_set_clk()
697 return -EINVAL; in px30_pwm_set_clk()
705 struct px30_cru *cru = priv->cru; in px30_saradc_get_clk()
706 u32 div, con; in px30_saradc_get_clk() local
708 con = readl(&cru->clksel_con[55]); in px30_saradc_get_clk()
709 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in px30_saradc_get_clk()
711 return DIV_TO_RATE(OSC_HZ, div); in px30_saradc_get_clk()
716 struct px30_cru *cru = priv->cru; in px30_saradc_set_clk()
720 assert(src_clk_div - 1 <= 2047); in px30_saradc_set_clk()
722 rk_clrsetreg(&cru->clksel_con[55], in px30_saradc_set_clk()
724 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in px30_saradc_set_clk()
731 struct px30_cru *cru = priv->cru; in px30_tsadc_get_clk()
732 u32 div, con; in px30_tsadc_get_clk() local
734 con = readl(&cru->clksel_con[54]); in px30_tsadc_get_clk()
735 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in px30_tsadc_get_clk()
737 return DIV_TO_RATE(OSC_HZ, div); in px30_tsadc_get_clk()
742 struct px30_cru *cru = priv->cru; in px30_tsadc_set_clk()
746 assert(src_clk_div - 1 <= 2047); in px30_tsadc_set_clk()
748 rk_clrsetreg(&cru->clksel_con[54], in px30_tsadc_set_clk()
750 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in px30_tsadc_set_clk()
757 struct px30_cru *cru = priv->cru; in px30_spi_get_clk()
758 u32 div, con; in px30_spi_get_clk() local
762 con = readl(&cru->clksel_con[53]); in px30_spi_get_clk()
763 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; in px30_spi_get_clk()
766 con = readl(&cru->clksel_con[53]); in px30_spi_get_clk()
767 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; in px30_spi_get_clk()
771 return -EINVAL; in px30_spi_get_clk()
774 return DIV_TO_RATE(priv->gpll_hz, div); in px30_spi_get_clk()
779 struct px30_cru *cru = priv->cru; in px30_spi_set_clk()
782 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_spi_set_clk()
783 assert(src_clk_div - 1 <= 127); in px30_spi_set_clk()
787 rk_clrsetreg(&cru->clksel_con[53], in px30_spi_set_clk()
790 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | in px30_spi_set_clk()
794 rk_clrsetreg(&cru->clksel_con[53], in px30_spi_set_clk()
797 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | in px30_spi_set_clk()
802 return -EINVAL; in px30_spi_set_clk()
810 struct px30_cru *cru = priv->cru; in px30_vop_get_clk()
811 u32 div, con, parent; in px30_vop_get_clk() local
816 con = readl(&cru->clksel_con[3]); in px30_vop_get_clk()
817 div = con & ACLK_VO_DIV_MASK; in px30_vop_get_clk()
818 parent = priv->gpll_hz; in px30_vop_get_clk()
821 con = readl(&cru->clksel_con[5]); in px30_vop_get_clk()
822 div = con & DCLK_VOPB_DIV_MASK; in px30_vop_get_clk()
823 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
826 con = readl(&cru->clksel_con[8]); in px30_vop_get_clk()
827 div = con & DCLK_VOPL_DIV_MASK; in px30_vop_get_clk()
828 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); in px30_vop_get_clk()
831 return -ENOENT; in px30_vop_get_clk()
834 return DIV_TO_RATE(parent, div); in px30_vop_get_clk()
839 struct px30_cru *cru = priv->cru; in px30_vop_set_clk()
846 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_vop_set_clk()
847 assert(src_clk_div - 1 <= 31); in px30_vop_set_clk()
848 rk_clrsetreg(&cru->clksel_con[3], in px30_vop_set_clk()
851 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); in px30_vop_set_clk()
857 src_clk_div = src_clk_div - 1; in px30_vop_set_clk()
861 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
862 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); in px30_vop_set_clk()
863 rk_clrsetreg(&cru->clksel_con[5], in px30_vop_set_clk()
868 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); in px30_vop_set_clk()
874 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
879 src_clk_div = src_clk_div - 1; in px30_vop_set_clk()
883 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
884 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); in px30_vop_set_clk()
886 rk_clrsetreg(&cru->clksel_con[8], in px30_vop_set_clk()
891 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); in px30_vop_set_clk()
895 return -EINVAL; in px30_vop_set_clk()
903 struct px30_cru *cru = priv->cru; in px30_bus_get_clk()
904 u32 div, con, parent; in px30_bus_get_clk() local
908 con = readl(&cru->clksel_con[23]); in px30_bus_get_clk()
909 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; in px30_bus_get_clk()
910 parent = priv->gpll_hz; in px30_bus_get_clk()
913 con = readl(&cru->clksel_con[24]); in px30_bus_get_clk()
914 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; in px30_bus_get_clk()
915 parent = priv->gpll_hz; in px30_bus_get_clk()
920 con = readl(&cru->clksel_con[24]); in px30_bus_get_clk()
921 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; in px30_bus_get_clk()
924 return -ENOENT; in px30_bus_get_clk()
927 return DIV_TO_RATE(parent, div); in px30_bus_get_clk()
933 struct px30_cru *cru = priv->cru; in px30_bus_set_clk()
942 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
943 assert(src_clk_div - 1 <= 31); in px30_bus_set_clk()
944 rk_clrsetreg(&cru->clksel_con[23], in px30_bus_set_clk()
947 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); in px30_bus_set_clk()
950 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
951 assert(src_clk_div - 1 <= 31); in px30_bus_set_clk()
952 rk_clrsetreg(&cru->clksel_con[24], in px30_bus_set_clk()
955 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); in px30_bus_set_clk()
960 assert(src_clk_div - 1 <= 3); in px30_bus_set_clk()
961 rk_clrsetreg(&cru->clksel_con[24], in px30_bus_set_clk()
963 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); in px30_bus_set_clk()
967 return -EINVAL; in px30_bus_set_clk()
975 struct px30_cru *cru = priv->cru; in px30_peri_get_clk()
976 u32 div, con, parent; in px30_peri_get_clk() local
980 con = readl(&cru->clksel_con[14]); in px30_peri_get_clk()
981 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; in px30_peri_get_clk()
982 parent = priv->gpll_hz; in px30_peri_get_clk()
985 con = readl(&cru->clksel_con[14]); in px30_peri_get_clk()
986 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; in px30_peri_get_clk()
987 parent = priv->gpll_hz; in px30_peri_get_clk()
990 return -ENOENT; in px30_peri_get_clk()
993 return DIV_TO_RATE(parent, div); in px30_peri_get_clk()
999 struct px30_cru *cru = priv->cru; in px30_peri_set_clk()
1002 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_peri_set_clk()
1003 assert(src_clk_div - 1 <= 31); in px30_peri_set_clk()
1011 rk_clrsetreg(&cru->clksel_con[14], in px30_peri_set_clk()
1014 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in px30_peri_set_clk()
1017 rk_clrsetreg(&cru->clksel_con[14], in px30_peri_set_clk()
1020 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); in px30_peri_set_clk()
1024 return -EINVAL; in px30_peri_set_clk()
1032 struct px30_cru *cru = priv->cru; in px30_otp_get_clk()
1033 u32 src, div, con, parent; in px30_otp_get_clk() local
1036 con = readl(&cru->clksel_con[56]); in px30_otp_get_clk()
1038 div = (con & CLK_OTP_S_DIV_CON_MASK) >> CLK_OTP_S_DIV_CON_SHIFT; in px30_otp_get_clk()
1040 return DIV_TO_RATE(priv->gpll_hz, div); in px30_otp_get_clk()
1042 return DIV_TO_RATE(OSC_HZ, div); in px30_otp_get_clk()
1047 con = readl(&cru->clksel_con[56]); in px30_otp_get_clk()
1048 div = (con & CLK_OTP_DIV_CON_MASK) >> CLK_OTP_DIV_CON_SHIFT; in px30_otp_get_clk()
1052 con = readl(&cru->clksel_con[56]); in px30_otp_get_clk()
1053 div = (con & CLK_OTP_USR_DIV_CON_MASK) >> in px30_otp_get_clk()
1058 return -ENOENT; in px30_otp_get_clk()
1061 return DIV_TO_RATE(parent, div); in px30_otp_get_clk()
1067 struct px30_cru *cru = priv->cru; in px30_otp_set_clk()
1068 u32 src, div, parent; in px30_otp_set_clk() local
1076 parent = priv->gpll_hz; in px30_otp_set_clk()
1078 div = DIV_ROUND_UP(parent, hz); in px30_otp_set_clk()
1079 rk_clrsetreg(&cru->clksel_con[56], in px30_otp_set_clk()
1082 (div - 1) << CLK_OTP_S_DIV_CON_SHIFT); in px30_otp_set_clk()
1088 div = DIV_ROUND_UP(OSC_HZ, hz); in px30_otp_set_clk()
1089 rk_clrsetreg(&cru->clksel_con[56], in px30_otp_set_clk()
1091 (div - 1) << CLK_OTP_DIV_CON_SHIFT); in px30_otp_set_clk()
1094 div = DIV_ROUND_UP(px30_otp_get_clk(priv, SCLK_OTP), hz); in px30_otp_set_clk()
1095 rk_clrsetreg(&cru->clksel_con[56], in px30_otp_set_clk()
1097 (div - 1) << CLK_OTP_USR_DIV_CON_SHIFT); in px30_otp_set_clk()
1101 return -EINVAL; in px30_otp_set_clk()
1109 struct px30_cru *cru = priv->cru; in px30_crypto_get_clk()
1110 u32 div, con, parent; in px30_crypto_get_clk() local
1114 con = readl(&cru->clksel_con[25]); in px30_crypto_get_clk()
1115 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in px30_crypto_get_clk()
1116 parent = priv->gpll_hz; in px30_crypto_get_clk()
1119 con = readl(&cru->clksel_con[25]); in px30_crypto_get_clk()
1120 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; in px30_crypto_get_clk()
1121 parent = priv->gpll_hz; in px30_crypto_get_clk()
1124 return -ENOENT; in px30_crypto_get_clk()
1127 return DIV_TO_RATE(parent, div); in px30_crypto_get_clk()
1133 struct px30_cru *cru = priv->cru; in px30_crypto_set_clk()
1136 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_crypto_set_clk()
1137 assert(src_clk_div - 1 <= 31); in px30_crypto_set_clk()
1145 rk_clrsetreg(&cru->clksel_con[25], in px30_crypto_set_clk()
1148 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in px30_crypto_set_clk()
1151 rk_clrsetreg(&cru->clksel_con[25], in px30_crypto_set_clk()
1154 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in px30_crypto_set_clk()
1158 return -EINVAL; in px30_crypto_set_clk()
1165 static ulong px30_mac_set_clk(struct clk *clk, uint hz) in px30_mac_set_clk() argument
1167 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in px30_mac_set_clk()
1168 struct px30_cru *cru = priv->cru; in px30_mac_set_clk()
1169 u32 con = readl(&cru->clksel_con[22]); in px30_mac_set_clk()
1171 u8 div; in px30_mac_set_clk() local
1178 pll_rate = priv->gpll_hz; in px30_mac_set_clk()
1184 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1185 assert(div < 32); in px30_mac_set_clk()
1186 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK, in px30_mac_set_clk()
1187 div << CLK_GMAC_DIV_SHIFT); in px30_mac_set_clk()
1189 return DIV_TO_RATE(pll_rate, div); in px30_mac_set_clk()
1192 static int px30_mac_set_speed_clk(struct clk *clk, uint hz) in px30_mac_set_speed_clk() argument
1194 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in px30_mac_set_speed_clk()
1195 struct px30_cru *cru = priv->cru; in px30_mac_set_speed_clk()
1199 return -EINVAL; in px30_mac_set_speed_clk()
1202 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK, in px30_mac_set_speed_clk()
1224 *rate = priv->gpll_hz; in px30_clk_get_gpll_rate()
1232 struct px30_cru *cru = priv->cru; in px30_clk_get_pll_rate()
1234 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_get_pll_rate()
1240 struct px30_cru *cru = priv->cru; in px30_clk_set_pll_rate()
1242 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) in px30_clk_set_pll_rate()
1243 return -EINVAL; in px30_clk_set_pll_rate()
1244 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); in px30_clk_set_pll_rate()
1249 struct px30_cru *cru = priv->cru; in px30_armclk_set_clk()
1256 return -EINVAL; in px30_armclk_set_clk()
1266 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1267 return -EINVAL; in px30_armclk_set_clk()
1268 rk_clrsetreg(&cru->clksel_con[0], in px30_armclk_set_clk()
1271 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1272 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1276 rk_clrsetreg(&cru->clksel_con[0], in px30_armclk_set_clk()
1279 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1280 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1283 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1284 return -EINVAL; in px30_armclk_set_clk()
1290 static ulong px30_clk_get_rate(struct clk *clk) in px30_clk_get_rate() argument
1292 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in px30_clk_get_rate()
1295 if (!priv->gpll_hz && clk->id > ARMCLK) { in px30_clk_get_rate()
1296 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in px30_clk_get_rate()
1297 return -ENOENT; in px30_clk_get_rate()
1300 debug("%s %ld\n", __func__, clk->id); in px30_clk_get_rate()
1301 switch (clk->id) { in px30_clk_get_rate()
1322 rate = px30_mmc_get_clk(priv, clk->id); in px30_clk_get_rate()
1325 rate = px30_sfc_get_clk(priv, clk->id); in px30_clk_get_rate()
1331 rate = px30_i2c_get_clk(priv, clk->id); in px30_clk_get_rate()
1334 rate = px30_i2s_get_clk(priv, clk->id); in px30_clk_get_rate()
1337 rate = px30_i2s1_mclk_get_clk(priv, clk->id); in px30_clk_get_rate()
1341 rate = px30_pwm_get_clk(priv, clk->id); in px30_clk_get_rate()
1351 rate = px30_spi_get_clk(priv, clk->id); in px30_clk_get_rate()
1357 rate = px30_vop_get_clk(priv, clk->id); in px30_clk_get_rate()
1363 rate = px30_bus_get_clk(priv, clk->id); in px30_clk_get_rate()
1367 rate = px30_peri_get_clk(priv, clk->id); in px30_clk_get_rate()
1371 rate = px30_otp_get_clk(priv, clk->id); in px30_clk_get_rate()
1375 rate = px30_crypto_get_clk(priv, clk->id); in px30_clk_get_rate()
1378 return -ENOENT; in px30_clk_get_rate()
1384 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) in px30_clk_set_rate() argument
1386 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in px30_clk_set_rate()
1389 if (!priv->gpll_hz && clk->id > ARMCLK) { in px30_clk_set_rate()
1390 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in px30_clk_set_rate()
1391 return -ENOENT; in px30_clk_set_rate()
1394 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_clk_set_rate()
1395 switch (clk->id) { in px30_clk_set_rate()
1400 if (priv->armclk_hz) in px30_clk_set_rate()
1402 priv->armclk_hz = rate; in px30_clk_set_rate()
1408 ret = px30_mmc_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1411 ret = px30_sfc_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1417 ret = px30_i2c_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1420 ret = px30_i2s_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1423 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1427 ret = px30_pwm_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1437 ret = px30_spi_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1443 ret = px30_vop_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1448 ret = px30_bus_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1452 ret = px30_peri_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1456 ret = px30_otp_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1460 ret = px30_crypto_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1465 ret = px30_mac_set_clk(clk, rate); in px30_clk_set_rate()
1468 ret = px30_mac_set_speed_clk(clk, rate); in px30_clk_set_rate()
1472 return -ENOENT; in px30_clk_set_rate()
1485 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1490 int rockchip_mmc_get_phase(struct clk *clk) in rockchip_mmc_get_phase() argument
1492 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_get_phase()
1493 struct px30_cru *cru = priv->cru; in rockchip_mmc_get_phase()
1498 rate = px30_clk_get_rate(clk); in rockchip_mmc_get_phase()
1503 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_get_phase()
1504 raw_value = readl(&cru->emmc_con[1]); in rockchip_mmc_get_phase()
1506 raw_value = readl(&cru->sdmmc_con[1]); in rockchip_mmc_get_phase()
1524 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) in rockchip_mmc_set_phase() argument
1526 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in rockchip_mmc_set_phase()
1527 struct px30_cru *cru = priv->cru; in rockchip_mmc_set_phase()
1532 rate = px30_clk_get_rate(clk); in rockchip_mmc_set_phase()
1542 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
1556 if (clk->id == SCLK_EMMC_SAMPLE) in rockchip_mmc_set_phase()
1557 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rockchip_mmc_set_phase()
1559 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rockchip_mmc_set_phase()
1562 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); in rockchip_mmc_set_phase()
1567 static int px30_clk_get_phase(struct clk *clk) in px30_clk_get_phase() argument
1571 debug("%s %ld\n", __func__, clk->id); in px30_clk_get_phase()
1572 switch (clk->id) { in px30_clk_get_phase()
1575 ret = rockchip_mmc_get_phase(clk); in px30_clk_get_phase()
1578 return -ENOENT; in px30_clk_get_phase()
1584 static int px30_clk_set_phase(struct clk *clk, int degrees) in px30_clk_set_phase() argument
1588 debug("%s %ld\n", __func__, clk->id); in px30_clk_set_phase()
1589 switch (clk->id) { in px30_clk_set_phase()
1592 ret = rockchip_mmc_set_phase(clk, degrees); in px30_clk_set_phase()
1595 return -ENOENT; in px30_clk_set_phase()
1602 static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) in px30_gmac_set_parent() argument
1604 struct px30_clk_priv *priv = dev_get_priv(clk->dev); in px30_gmac_set_parent()
1605 struct px30_cru *cru = priv->cru; in px30_gmac_set_parent()
1607 if (parent->id == SCLK_GMAC_SRC) { in px30_gmac_set_parent()
1609 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, in px30_gmac_set_parent()
1613 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, in px30_gmac_set_parent()
1619 static int px30_clk_set_parent(struct clk *clk, struct clk *parent) in px30_clk_set_parent() argument
1621 switch (clk->id) { in px30_clk_set_parent()
1623 return px30_gmac_set_parent(clk, parent); in px30_clk_set_parent()
1625 return -ENOENT; in px30_clk_set_parent()
1645 priv->sync_kernel = false; in px30_clk_probe()
1646 if (!priv->armclk_enter_hz) { in px30_clk_probe()
1647 priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL); in px30_clk_probe()
1648 priv->armclk_init_hz = priv->armclk_enter_hz; in px30_clk_probe()
1654 priv->armclk_init_hz = APLL_HZ; in px30_clk_probe()
1657 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in px30_clk_probe()
1662 priv->sync_kernel = true; in px30_clk_probe()
1664 if (!priv->gpll_hz) { in px30_clk_probe()
1665 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); in px30_clk_probe()
1679 priv->cru = dev_read_addr_ptr(dev); in px30_clk_ofdata_to_platdata()
1698 priv->glb_srst_fst_value = offsetof(struct px30_cru, in px30_clk_bind()
1700 priv->glb_srst_snd_value = offsetof(struct px30_cru, in px30_clk_bind()
1702 sys_child->priv = priv; in px30_clk_bind()
1711 sf_priv->sf_reset_offset = offsetof(struct px30_cru, in px30_clk_bind()
1713 sf_priv->sf_reset_num = 12; in px30_clk_bind()
1714 sf_child->priv = sf_priv; in px30_clk_bind()
1721 { .compatible = "rockchip,px30-cru" },
1738 struct px30_pmucru *pmucru = priv->pmucru; in px30_pclk_pmu_get_pmuclk()
1739 u32 div, con; in px30_pclk_pmu_get_pmuclk() local
1741 con = readl(&pmucru->pmu_clksel_con[0]); in px30_pclk_pmu_get_pmuclk()
1742 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; in px30_pclk_pmu_get_pmuclk()
1744 return DIV_TO_RATE(priv->gpll_hz, div); in px30_pclk_pmu_get_pmuclk()
1749 struct px30_pmucru *pmucru = priv->pmucru; in px30_pclk_pmu_set_pmuclk()
1752 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pclk_pmu_set_pmuclk()
1753 assert(src_clk_div - 1 <= 31); in px30_pclk_pmu_set_pmuclk()
1755 rk_clrsetreg(&pmucru->pmu_clksel_con[0], in px30_pclk_pmu_set_pmuclk()
1757 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); in px30_pclk_pmu_set_pmuclk()
1764 struct px30_pmucru *pmucru = priv->pmucru; in px30_gpll_get_pmuclk()
1766 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); in px30_gpll_get_pmuclk()
1773 struct px30_pmucru *pmucru = priv->pmucru; in px30_gpll_set_pmuclk()
1774 u32 div; in px30_gpll_set_pmuclk() local
1781 "clock-controller@ff2b0000", in px30_gpll_set_pmuclk()
1789 if (priv->gpll_hz == hz) in px30_gpll_set_pmuclk()
1790 return priv->gpll_hz; in px30_gpll_set_pmuclk()
1792 cru_priv->gpll_hz = priv->gpll_hz; in px30_gpll_set_pmuclk()
1793 div = DIV_ROUND_UP(hz, priv->gpll_hz); in px30_gpll_set_pmuclk()
1814 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); in px30_gpll_set_pmuclk()
1815 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); in px30_gpll_set_pmuclk()
1816 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); in px30_gpll_set_pmuclk()
1817 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); in px30_gpll_set_pmuclk()
1818 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); in px30_gpll_set_pmuclk()
1819 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); in px30_gpll_set_pmuclk()
1821 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); in px30_gpll_set_pmuclk()
1822 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); in px30_gpll_set_pmuclk()
1823 px30_nandc_set_clk(cru_priv, nandc_rate / div); in px30_gpll_set_pmuclk()
1824 px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate / div); in px30_gpll_set_pmuclk()
1827 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); in px30_gpll_set_pmuclk()
1828 priv->gpll_hz = px30_gpll_get_pmuclk(priv); in px30_gpll_set_pmuclk()
1829 cru_priv->gpll_hz = priv->gpll_hz; in px30_gpll_set_pmuclk()
1844 return priv->gpll_hz; in px30_gpll_set_pmuclk()
1847 static ulong px30_pmuclk_get_rate(struct clk *clk) in px30_pmuclk_get_rate() argument
1849 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); in px30_pmuclk_get_rate()
1852 debug("%s %ld\n", __func__, clk->id); in px30_pmuclk_get_rate()
1853 switch (clk->id) { in px30_pmuclk_get_rate()
1861 return -ENOENT; in px30_pmuclk_get_rate()
1867 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) in px30_pmuclk_set_rate() argument
1869 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); in px30_pmuclk_set_rate()
1872 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_pmuclk_set_rate()
1873 switch (clk->id) { in px30_pmuclk_set_rate()
1881 return -ENOENT; in px30_pmuclk_set_rate()
1900 "clock-controller@ff2b0000", &cru_dev); in px30_clk_init()
1911 priv->gpll_hz = px30_gpll_get_pmuclk(priv); in px30_clk_init()
1912 if (priv->gpll_hz != GPLL_HZ) { in px30_clk_init()
1918 cru_priv->gpll_hz = priv->gpll_hz; in px30_clk_init()
1945 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in px30_pmuclk_probe()
1957 priv->pmucru = dev_read_addr_ptr(dev); in px30_pmuclk_ofdata_to_platdata()
1963 { .compatible = "rockchip,px30-pmucru" },
1978 * soc_clk_dump() - Print clock frequencies
1981 * Implementation for the clk dump command.
1988 struct clk clk; in soc_clk_dump() local
2010 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
2011 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
2012 priv->armclk_enter_hz / 1000, in soc_clk_dump()
2013 priv->armclk_init_hz / 1000, in soc_clk_dump()
2014 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
2015 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
2018 if (clk_dump->name) { in soc_clk_dump()
2019 clk.id = clk_dump->id; in soc_clk_dump()
2020 if (clk_dump->is_cru) in soc_clk_dump()
2021 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
2023 ret = clk_request(pmucru_dev, &clk); in soc_clk_dump()
2027 rate = clk_get_rate(&clk); in soc_clk_dump()
2028 clk_free(&clk); in soc_clk_dump()
2031 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
2034 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
2038 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
2041 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()