Lines Matching +full:1 +full:hz
51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
62 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
63 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
64 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
65 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
66 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
67 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
68 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
86 PX30_CPUCLK_RATE(1200000000, 1, 5),
87 PX30_CPUCLK_RATE(1008000000, 1, 5),
88 PX30_CPUCLK_RATE(816000000, 1, 3),
89 PX30_CPUCLK_RATE(600000000, 1, 3),
90 PX30_CPUCLK_RATE(408000000, 1, 1),
111 u32 postdiv1, postdiv2 = 1; in pll_clk_set_by_auto()
120 printf("%s: the frequency can't be 0 Hz\n", __func__); in pll_clk_set_by_auto()
143 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { in pll_clk_set_by_auto()
150 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_clk_set_by_auto()
164 printf("%s: Failed to match output frequency %u bestis %u Hz\n", in pll_clk_set_by_auto()
200 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
202 * If DSMPD = 1 (DSM is disabled, "integer mode")
231 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", in rkclk_set_pll()
245 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
247 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
257 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
260 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) in rkclk_set_pll()
261 udelay(1); in rkclk_set_pll()
327 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2c_set_clk() argument
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
333 assert(src_clk_div - 1 <= 127); in px30_i2c_set_clk()
340 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in px30_i2c_set_clk()
347 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in px30_i2c_set_clk()
354 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in px30_i2c_set_clk()
361 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in px30_i2c_set_clk()
380 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
399 n1 = 1; in rational_best_approximation()
400 d0 = 1; in rational_best_approximation()
453 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2s_set_clk() argument
460 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
461 GENMASK(16 - 1, 0), in px30_i2s_set_clk()
462 GENMASK(16 - 1, 0), in px30_i2s_set_clk()
500 ulong hz) in px30_i2s1_mclk_set_clk() argument
504 if (hz == 12000000) { in px30_i2s1_mclk_set_clk()
508 px30_i2s_set_clk(priv, SCLK_I2S1, hz); in px30_i2s1_mclk_set_clk()
539 assert(src_clk_div - 1 <= 31); in px30_nandc_set_clk()
546 (src_clk_div - 1) << NANDC_DIV_SHIFT); in px30_nandc_set_clk()
611 (src_clk_div - 1) << EMMC_DIV_SHIFT); in px30_mmc_set_clk()
616 (src_clk_div - 1) << EMMC_DIV_SHIFT); in px30_mmc_set_clk()
618 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, in px30_mmc_set_clk()
645 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); in px30_sfc_set_clk()
672 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_pwm_set_clk() argument
677 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
678 assert(src_clk_div - 1 <= 127); in px30_pwm_set_clk()
685 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | in px30_pwm_set_clk()
692 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | in px30_pwm_set_clk()
714 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_saradc_set_clk() argument
719 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
720 assert(src_clk_div - 1 <= 2047); in px30_saradc_set_clk()
724 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in px30_saradc_set_clk()
740 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_tsadc_set_clk() argument
745 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_tsadc_set_clk()
746 assert(src_clk_div - 1 <= 2047); in px30_tsadc_set_clk()
750 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in px30_tsadc_set_clk()
777 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_spi_set_clk() argument
782 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_spi_set_clk()
783 assert(src_clk_div - 1 <= 127); in px30_spi_set_clk()
790 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | in px30_spi_set_clk()
797 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | in px30_spi_set_clk()
837 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_vop_set_clk() argument
846 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_vop_set_clk()
847 assert(src_clk_div - 1 <= 31); in px30_vop_set_clk()
851 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); in px30_vop_set_clk()
854 if (hz < PX30_VOP_PLL_LIMIT) { in px30_vop_set_clk()
855 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); in px30_vop_set_clk()
857 src_clk_div = src_clk_div - 1; in px30_vop_set_clk()
859 src_clk_div = 1; in px30_vop_set_clk()
861 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
862 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); in px30_vop_set_clk()
868 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); in px30_vop_set_clk()
872 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { in px30_vop_set_clk()
873 src_clk_div = npll_hz / hz; in px30_vop_set_clk()
874 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
876 if (hz < PX30_VOP_PLL_LIMIT) { in px30_vop_set_clk()
877 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); in px30_vop_set_clk()
879 src_clk_div = src_clk_div - 1; in px30_vop_set_clk()
881 src_clk_div = 1; in px30_vop_set_clk()
883 assert(src_clk_div - 1 <= 255); in px30_vop_set_clk()
884 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); in px30_vop_set_clk()
891 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); in px30_vop_set_clk()
931 ulong hz) in px30_bus_set_clk() argument
942 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
943 assert(src_clk_div - 1 <= 31); in px30_bus_set_clk()
947 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); in px30_bus_set_clk()
950 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_bus_set_clk()
951 assert(src_clk_div - 1 <= 31); in px30_bus_set_clk()
955 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); in px30_bus_set_clk()
959 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); in px30_bus_set_clk()
960 assert(src_clk_div - 1 <= 3); in px30_bus_set_clk()
963 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); in px30_bus_set_clk()
997 ulong hz) in px30_peri_set_clk() argument
1002 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_peri_set_clk()
1003 assert(src_clk_div - 1 <= 31); in px30_peri_set_clk()
1014 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); in px30_peri_set_clk()
1020 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); in px30_peri_set_clk()
1065 ulong hz) in px30_otp_set_clk() argument
1071 if ((OSC_HZ % hz) == 0) { in px30_otp_set_clk()
1075 src = 1; in px30_otp_set_clk()
1078 div = DIV_ROUND_UP(parent, hz); in px30_otp_set_clk()
1082 (div - 1) << CLK_OTP_S_DIV_CON_SHIFT); in px30_otp_set_clk()
1088 div = DIV_ROUND_UP(OSC_HZ, hz); in px30_otp_set_clk()
1091 (div - 1) << CLK_OTP_DIV_CON_SHIFT); in px30_otp_set_clk()
1094 div = DIV_ROUND_UP(px30_otp_get_clk(priv, SCLK_OTP), hz); in px30_otp_set_clk()
1097 (div - 1) << CLK_OTP_USR_DIV_CON_SHIFT); in px30_otp_set_clk()
1131 ulong hz) in px30_crypto_set_clk() argument
1136 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_crypto_set_clk()
1137 assert(src_clk_div - 1 <= 31); in px30_crypto_set_clk()
1148 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in px30_crypto_set_clk()
1154 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in px30_crypto_set_clk()
1165 static ulong px30_mac_set_clk(struct clk *clk, uint hz) in px30_mac_set_clk() argument
1181 if (!hz) in px30_mac_set_clk()
1182 hz = 50000000; in px30_mac_set_clk()
1184 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1192 static int px30_mac_set_speed_clk(struct clk *clk, uint hz) in px30_mac_set_speed_clk() argument
1197 if (hz != 2500000 && hz != 25000000) { in px30_mac_set_speed_clk()
1198 debug("Unsupported mac speed:%d\n", hz); in px30_mac_set_speed_clk()
1203 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT); in px30_mac_set_speed_clk()
1238 enum px30_pll_id pll_id, ulong hz) in px30_clk_set_pll_rate() argument
1242 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) in px30_clk_set_pll_rate()
1247 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) in px30_armclk_set_clk() argument
1253 rate = get_cpu_settings(hz); in px30_armclk_set_clk()
1262 * core hz : apll = 1:1 in px30_armclk_set_clk()
1265 if (old_rate > hz) { in px30_armclk_set_clk()
1266 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1275 } else if (old_rate < hz) { in px30_armclk_set_clk()
1283 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) in px30_armclk_set_clk()
1504 raw_value = readl(&cru->emmc_con[1]); in rockchip_mmc_get_phase()
1506 raw_value = readl(&cru->sdmmc_con[1]); in rockchip_mmc_get_phase()
1508 raw_value >>= 1; in rockchip_mmc_get_phase()
1555 raw_value <<= 1; in rockchip_mmc_set_phase()
1557 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rockchip_mmc_set_phase()
1559 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rockchip_mmc_set_phase()
1747 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) in px30_pclk_pmu_set_pmuclk() argument
1752 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pclk_pmu_set_pmuclk()
1753 assert(src_clk_div - 1 <= 31); in px30_pclk_pmu_set_pmuclk()
1757 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); in px30_pclk_pmu_set_pmuclk()
1769 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) in px30_gpll_set_pmuclk() argument
1789 if (priv->gpll_hz == hz) in px30_gpll_set_pmuclk()
1793 div = DIV_ROUND_UP(hz, priv->gpll_hz); in px30_gpll_set_pmuclk()
1827 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); in px30_gpll_set_pmuclk()