Lines Matching +full:r8a73a4 +full:- +full:mstp +full:- +full:clocks
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <clk-uclass.h>
21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
33 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
34 * R-Car Gen2, R-Car Gen3, and RZ/G1.
35 * These are NOT valid for R-Car Gen1 and RZ/A1!
63 #define RMSTPCR(i) (smstpcr[i] - 0x20)
65 /* Modem Module Stop Control Register offsets (r8a73a4) */
83 * Definitions of CPG Core Clocks
86 * - Clock outputs exported to DT
87 * - External input clocks
88 * - Internal CPG clocks
96 unsigned int parent; /* Core Clocks only */
124 * Definitions of Module Clocks
129 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
132 /* Convert from sparse base-100 to packed index space */
133 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
161 /* External Input Clocks */
165 /* Internal Core Clocks */
182 /* Module Clocks */
191 /* Internal Core Clocks */
243 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
244 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
245 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
255 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
256 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
257 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
269 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
270 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
271 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
272 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
273 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
274 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
276 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
277 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
358 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
359 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
360 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
363 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
369 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
380 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
381 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
382 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
383 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
384 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
385 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
386 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
387 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
388 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
389 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
390 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
391 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
392 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
393 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
394 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
402 /* Internal Core Clocks */
463 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
464 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
465 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
477 DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1),
478 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
480 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
481 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
541 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
542 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
543 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
546 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
552 DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4),
563 DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4),
564 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
565 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
566 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
567 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
568 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
569 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
570 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
571 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
572 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
573 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
574 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
575 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
576 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
577 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
587 *-------------------------------------------------------------------
656 *-------------------------------------------------------------------
684 return (clk->id >> 16) == CPG_MOD; in gen3_clk_is_mod()
689 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); in gen3_clk_get_mod()
690 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_get_mod()
694 return -EINVAL; in gen3_clk_get_mod()
696 for (i = 0; i < priv->mod_clk_size; i++) { in gen3_clk_get_mod()
697 if (priv->mod_clk[i].id != MOD_CLK_ID(clkid)) in gen3_clk_get_mod()
700 *mssr = &priv->mod_clk[i]; in gen3_clk_get_mod()
704 return -ENODEV; in gen3_clk_get_mod()
709 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); in gen3_clk_get_core()
710 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_get_core()
714 return -EINVAL; in gen3_clk_get_core()
716 for (i = 0; i < priv->core_clk_size; i++) { in gen3_clk_get_core()
717 if (priv->core_clk[i].id != clkid) in gen3_clk_get_core()
720 *core = &priv->core_clk[i]; in gen3_clk_get_core()
724 return -ENODEV; in gen3_clk_get_core()
738 parent->id = mssr->parent; in gen3_clk_get_parent()
744 if (core->type == CLK_TYPE_IN) in gen3_clk_get_parent()
745 parent->id = ~0; /* Top-level clock */ in gen3_clk_get_parent()
747 parent->id = core->parent; in gen3_clk_get_parent()
750 parent->dev = clk->dev; in gen3_clk_get_parent()
757 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); in gen3_clk_endisable()
758 const unsigned long clkid = clk->id & 0xffff; in gen3_clk_endisable()
764 return -EINVAL; in gen3_clk_endisable()
766 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__, in gen3_clk_endisable()
770 clrbits_le32(priv->base + SMSTPCR(reg), bitmask); in gen3_clk_endisable()
771 return wait_for_bit_le32(priv->base + MSTPSR(reg), in gen3_clk_endisable()
774 setbits_le32(priv->base + SMSTPCR(reg), bitmask); in gen3_clk_endisable()
791 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); in gen3_clk_get_rate()
795 priv->cpg_pll_config; in gen3_clk_get_rate()
799 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); in gen3_clk_get_rate()
818 switch (core->type) { in gen3_clk_get_rate()
820 if (core->id == CLK_EXTAL) { in gen3_clk_get_rate()
821 rate = clk_get_rate(&priv->clk_extal); in gen3_clk_get_rate()
827 if (core->id == CLK_EXTALR) { in gen3_clk_get_rate()
828 rate = clk_get_rate(&priv->clk_extalr); in gen3_clk_get_rate()
834 return -EINVAL; in gen3_clk_get_rate()
837 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; in gen3_clk_get_rate()
840 core->parent, pll_config->extal_div, rate); in gen3_clk_get_rate()
844 value = readl(priv->base + CPG_PLL0CR); in gen3_clk_get_rate()
848 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate()
852 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate()
855 core->parent, pll_config->pll1_mult, rate); in gen3_clk_get_rate()
859 value = readl(priv->base + CPG_PLL2CR); in gen3_clk_get_rate()
863 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate()
867 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; in gen3_clk_get_rate()
870 core->parent, pll_config->pll3_mult, rate); in gen3_clk_get_rate()
874 value = readl(priv->base + CPG_PLL4CR); in gen3_clk_get_rate()
878 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate()
882 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; in gen3_clk_get_rate()
885 core->parent, core->mult, core->div, rate); in gen3_clk_get_rate()
889 value = readl(priv->base + core->offset); in gen3_clk_get_rate()
900 core->parent, cpg_sd_div_table[i].div, rate); in gen3_clk_get_rate()
905 return -EINVAL; in gen3_clk_get_rate()
910 return -ENOENT; in gen3_clk_get_rate()
920 if (args->args_count != 2) { in gen3_clk_of_xlate()
921 debug("Invaild args_count: %d\n", args->args_count); in gen3_clk_of_xlate()
922 return -EINVAL; in gen3_clk_of_xlate()
925 clk->id = (args->args[0] << 16) | args->args[1]; in gen3_clk_of_xlate()
951 priv->base = (struct gen3_base *)devfdt_get_addr(dev); in gen3_clk_probe()
952 if (!priv->base) in gen3_clk_probe()
953 return -EINVAL; in gen3_clk_probe()
957 priv->core_clk = r8a7795_core_clks; in gen3_clk_probe()
958 priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks); in gen3_clk_probe()
959 priv->mod_clk = r8a7795_mod_clks; in gen3_clk_probe()
960 priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks); in gen3_clk_probe()
961 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in gen3_clk_probe()
962 "renesas,r8a7795-rst"); in gen3_clk_probe()
967 priv->core_clk = r8a7796_core_clks; in gen3_clk_probe()
968 priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks); in gen3_clk_probe()
969 priv->mod_clk = r8a7796_mod_clks; in gen3_clk_probe()
970 priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks); in gen3_clk_probe()
971 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in gen3_clk_probe()
972 "renesas,r8a7796-rst"); in gen3_clk_probe()
977 return -EINVAL; in gen3_clk_probe()
980 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); in gen3_clk_probe()
982 return -EINVAL; in gen3_clk_probe()
986 priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; in gen3_clk_probe()
987 if (!priv->cpg_pll_config->extal_div) in gen3_clk_probe()
988 return -EINVAL; in gen3_clk_probe()
990 ret = clk_get_by_name(dev, "extal", &priv->clk_extal); in gen3_clk_probe()
994 ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr); in gen3_clk_probe()
1002 { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
1003 { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },