Lines Matching refs:div1
228 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
233 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_dci_rate()
236 zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); in zynq_clk_get_dci_rate()
245 u32 div1 = 1; in zynq_clk_get_peripheral_rate() local
255 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; in zynq_clk_get_peripheral_rate()
256 if (!div1) in zynq_clk_get_peripheral_rate()
257 div1 = 1; in zynq_clk_get_peripheral_rate()
267 div1); in zynq_clk_get_peripheral_rate()
290 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs() argument
304 *div1 = d1; in zynq_clk_calc_peripheral_two_divs()
319 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
332 &div0, &div1); in zynq_clk_set_peripheral_rate()
333 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; in zynq_clk_set_peripheral_rate()