34  * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
53 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)  in ast2500_get_mpll_rate()  argument
61 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);  in ast2500_get_mpll_rate()
68 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)  in ast2500_get_hpll_rate()  argument
76 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);  in ast2500_get_hpll_rate()
97 	 * especially when CLKIN = 25 MHz. The settings are in  in ast2500_get_uart_clk_rate()
100 	 * This has only been tested with default settings and CLKIN = 24 MHz.  in ast2500_get_uart_clk_rate()
119 	ulong clkin = ast2500_get_clkin(priv->scu);  in ast2500_clk_get_rate()  local
129 		rate = ast2500_get_hpll_rate(clkin,  in ast2500_clk_get_rate()
133 		rate = ast2500_get_mpll_rate(clkin,  in ast2500_clk_get_rate()
141 			rate = ast2500_get_hpll_rate(clkin,  in ast2500_clk_get_rate()
223 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_ddr()  local
231 	ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_ddr()
244 	return ast2500_get_mpll_rate(clkin, mpll_reg);  in ast2500_configure_ddr()
249 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_mac()  local
250 	ulong hpll_rate = ast2500_get_hpll_rate(clkin,  in ast2500_configure_mac()
336 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_d2pll()  local
351 	new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_d2pll()